tlul_adapter_sram
Adapt TL-UL device traffic onto an SRAM-like memory port.
Translate Get/Put into req/we/addr/wdata/wmask transactions and track outstanding responses. Responses return in request order: a write responds once accepted, a read once rvalid_i returns its data, and a rejected request without an SRAM access.
BaseAddr is intentionally omitted so multiple memory maps may be used in an SoC. Aliasing can happen if the TL-UL crossbar target size is bigger than the SRAM.
At most one of ENABLE_DATA_INTG_GEN and ENABLE_DATA_INTG_PT may be enabled; there is no legal case where both are true. Both may be disabled when a non-security-critical memory has no stored integrity and an upstream entity already returns integrity. SRAM_DW must be a multiple of the TL width.
The remaining parameters select optional features:
- BYTE_ACCESS enables sub-word writes and results in read-modify-write for integrity regeneration when ENABLE_DATA_INTG_PT is set and ERR_ON_WRITE is clear.
- ERR_ON_WRITE and ERR_ON_READ automatically error disallowed accesses.
- CMD_INTG_CHECK enables command and A-channel data integrity checking.
- ENABLE_RSP_INTG_GEN and ENABLE_DATA_INTG_GEN generate response and data integrity.
- ENABLE_DATA_INTG_PT passes write data integrity to the SRAM and returns the stored integrity with read data.
- SEC_FIFO_PTR uses redundant FIFO pointers.
- ENABLE_READBACK reads back and checks written or read data.
- DATA_XOR_ADDR removes an address XOR that the memory applied to read data, so a faulted read address shows up as an integrity error; it takes effect only with ENABLE_DATA_INTG_PT.
- SRAM_BUS_BANK_AW is the SRAM bank address width, used only when DATA_XOR_ADDR is set.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
SRAM_AW | int | 12 | SRAM word-address width. |
SRAM_DW | int | 32 | SRAM data width; must be a multiple of TL_DW. |
OUTSTANDING | int | 1 | Maximum outstanding SRAM transactions. |
SRAM_BUS_BANK_AW | int | 12 | SRAM bank address width; used when DATA_XOR_ADDR=1. |
BYTE_ACCESS | bit | 1 | Allow sub-word writes; may RMW if ENABLE_DATA_INTG_PT. |
ERR_ON_WRITE | bit | 0 | Reject writes with a bus error. |
ERR_ON_READ | bit | 0 | Reject reads with a bus error. |
CMD_INTG_CHECK | bit | 0 | Check A-channel command and data integrity. |
ENABLE_RSP_INTG_GEN | bit | 0 | Generate D-channel response integrity. |
ENABLE_DATA_INTG_GEN | bit | 0 | Generate D-channel data integrity. |
ENABLE_DATA_INTG_PT | bit | 0 | Pass data integrity through to the SRAM port. |
SEC_FIFO_PTR | bit | 0 | Use redundant pointers in all three FIFOs. |
ENABLE_READBACK | bit | 0 | Read back and check written or read data. |
DATA_XOR_ADDR | bit | 0 | XOR read data with the SRAM bank address. |
WidthMult | int | SRAM_DW / top_pkg::TL_DW | TL beats packed per SRAM word. |
IntgWidth | int | tlul_pkg::DATA_INTG_WIDTH * WidthMult | Integrity bits per SRAM word with PT. |
DataOutW | int | ENABLE_DATA_INTG_PT ? SRAM_DW + IntgWidth : SRAM_DW | Width of wdata_o, wmask_o and rdata_i. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | | System clock. |
rst_ni | input | | Active-low reset. |
tl_i | input | tl_h2d_t | TL-UL host-to-device request. |
tl_o | output | tl_d2h_t | TL-UL device-to-host response. |
en_ifetch_i | input | mubi4_t | MuBi4True allows instruction-fetch Gets. |
req_o | output | logic | SRAM request valid. |
req_type_o | output | mubi4_t | A_USER.INSTR_TYPE of the request. |
gnt_i | input | | SRAM grant. |
we_o | output | logic | SRAM write enable. |
addr_o | output | logic [SRAM_AW-1:0] | SRAM word address. |
wdata_o | output | logic [DataOutW-1:0] | SRAM write data (and optional integrity). |
wmask_o | output | logic [DataOutW-1:0] | SRAM write mask (and optional integrity). |
intg_error_o | output | logic | Integrity or FIFO pointer error; sticky. |
user_rsvd_o | output | logic [RSVD_WIDTH-1:0] | Reserved user bits toward the SRAM side. |
rdata_i | input | [DataOutW-1:0] | SRAM read data (and optional integrity). |
rvalid_i | input | | SRAM read-data valid. |
rerror_i | input | [1:0] | [1] uncorrectable, sets D_ERROR; [0] unused. |
compound_txn_in_progress_o | output | logic | RMW write or readback request driven. |
readback_en_i | input | mubi4_t | MuBi4 readback enable; needs ENABLE_READBACK. |
readback_error_o | output | logic | Readback failure; sticky until reset. |
wr_collision_i | input | logic | SRAM write collision; assertions only. |
write_pending_i | input | logic | SRAM write pending; assertions only. |