tlul_fifo_sync

Buffer a TL-UL link with synchronous request and response FIFOs.

Instantiate separate request and response FIFOs to add elasticity on a TL-UL bus. The response FIFO stores d_data as zero for any opcode other than ACCESS_ACK_DATA. REQ_PASS and RSP_PASS allow fall-through when the corresponding FIFO is empty. SPARE_REQ_W and SPARE_RSP_W carry optional sideband bits alongside each channel.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`REQ_PASS`	`bit`	`1'b1`	Allow A-channel fall-through when empty.
`RSP_PASS`	`bit`	`1'b1`	Allow D-channel fall-through when empty.
`REQ_DEPTH`	`int unsigned`	`2`	Depth of the host-to-device request FIFO; 0 bypasses it and requires REQ_PASS.
`RSP_DEPTH`	`int unsigned`	`2`	Depth of the device-to-host response FIFO; 0 bypasses it and requires RSP_PASS.
`SPARE_REQ_W`	`int unsigned`	`1`	Width of spare bits with each request.
`SPARE_RSP_W`	`int unsigned`	`1`	Width of spare bits with each response.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input		System clock.
`rst_ni`	input		Active-low reset.
`tl_h_i`	input	`tlul_pkg::tl_h2d_t`	Host-side TL-UL request.
`tl_h_o`	output	`tlul_pkg::tl_d2h_t`	Host-side TL-UL response.
`tl_d_o`	output	`tlul_pkg::tl_h2d_t`	Device-side TL-UL request.
`tl_d_i`	input	`tlul_pkg::tl_d2h_t`	Device-side TL-UL response.
`spare_req_i`	input	`[SPARE_REQ_W-1:0]`	Spare request bits entering with tl_h_i.
`spare_req_o`	output	`[SPARE_REQ_W-1:0]`	Spare request bits leaving with tl_d_o.
`spare_rsp_i`	input	`[SPARE_RSP_W-1:0]`	Spare response bits entering with tl_d_i.
`spare_rsp_o`	output	`[SPARE_RSP_W-1:0]`	Spare response bits leaving with tl_h_o.