tlul_sram_byte

Handle TL-UL byte writes with integrity-aware read-modify-write.

When a write with a partial mask arrives and ENABLE_INTG is set, read the full word first, merge the written bytes, regenerate data integrity, and write the full word back. When RMW is not required, mux the incoming transaction straight through. compound_txn_in_progress_o is high while this module drives its own RMW write or readback request downstream.

If error_i is set on an incoming transaction, do not attempt byte-write handling. Feed the transaction through and allow the system to error back, and feed the error indication through on error_o.

ENABLE_READBACK enables readback checks on all transactions while readback_en_i is MuBi4True, and requires ENABLE_INTG == 1. alert_o reports readback mismatches and invalid FSM states. When ENABLE_INTG is clear, every signal passes straight through and alert_o and compound_txn_in_progress_o are 0.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`ENABLE_INTG`	`bit`	`0`	Handle partial-mask writes with integrity RMW.
`OUTSTANDING`	`int`	`1`	Maximum outstanding transactions tracked.
`ENABLE_READBACK`	`bit`	`0`	Readback-check transactions; needs ENABLE_INTG.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input		System clock.
`rst_ni`	input		Active-low reset.
`tl_i`	input	`tl_h2d_t`	Upstream TL-UL request.
`tl_o`	output	`tl_d2h_t`	Upstream TL-UL response.
`tl_sram_o`	output	`tl_h2d_t`	Downstream request toward the memory.
`tl_sram_i`	input	`tl_d2h_t`	Downstream response from the memory.
`error_i`	input		Error detected on the incoming request; it passes through without RMW.
`error_o`	output	`logic`	error_i, masked while the host is stalled.
`alert_o`	output	`logic`	Readback mismatch or invalid FSM state.
`compound_txn_in_progress_o`	output	`logic`	High while an RMW write or readback request is driven downstream.
`readback_en_i`	input	`prim_mubi_pkg::mubi4_t`	MuBi4 readback enable; sampled while the bus is idle.
`wr_collision_i`	input	`logic`	SRAM write collision; used only by assertions.
`write_pending_i`	input	`logic`	SRAM write pending; used only by assertions.