avsbus_async_fifo

Cross AVSBus data between the write and read clock domains in an async FIFO.

Gray-coded pointers cross each way through prim_sync3 synchronizers, so DEPTH must be a power of two. Each side takes its own synchronized reset. vacant_slots_o and full_slots_o report occupancy in the write domain for flow control.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`DEPTH`	`int unsigned`	`8`	FIFO depth in entries; must be a power of two.
`WIDTH`	`int unsigned`	`32`	FIFO data width in bits.

Ports

Table 2. Ports
Name	Direction	Type	Description
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low; unused.
`test_mode_i`	input	`logic`	DFT test mode; unused.
`rst_wr_clk_syncd_ni`	input	`logic`	Write-side reset, synchronized to wr_clk_i.
`wr_clk_i`	input	`logic`	Write clock.
`wr_en_i`	input	`logic`	Write enable; ignored while wr_full_o is high.
`wr_data_i`	input	`logic [WIDTH-1:0]`	Write data.
`wr_full_o`	output	`logic`	FIFO full in the write domain.
`wr_empty_o`	output	`logic`	FIFO empty in the write domain.
`rst_rd_clk_syncd_ni`	input	`logic`	Read-side reset, synchronized to rd_clk_i.
`rd_clk_i`	input	`logic`	Read clock.
`rd_en_i`	input	`logic`	Read enable; ignored while rd_empty_o is high.
`rd_data_o`	output	`logic [WIDTH-1:0]`	Head entry, read combinationally before rd_en_i.
`rd_empty_o`	output	`logic`	FIFO empty in the read domain.
`vacant_slots_o`	output	`logic [$clog2(DEPTH):0]`	Free entries, computed in the wr_clk_i domain.
`full_slots_o`	output	`logic [$clog2(DEPTH):0]`	Occupied entries, computed in the wr_clk_i domain.