cross_trigger_port

Bridge core cross-trigger pulses to GPIO pads in wire-OR or point-to-point mode with AXI-Lite CSRs.

Wraps cross_trigger_port_core; CSRs program mode, invert, stretch, and handshake reset. ct_src_i is the synchronous core source pulse; ct_dst_o is the registered destination pulse; busy_o marks a transfer in progress. Pad ports cover CT_Req_out/in and CT_Ack_in/out with dout, dout_en, din, and din_en as required by mode. The CSR MODE field selects wire-OR at 0 and point-to-point at 1; it resets to wire-OR.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock for the AXI-Lite CSRs and the port logic.
`rst_ni`	input	`logic`	Active-low asynchronous system reset.
`axil_req_i`	input	`axil_req_t`	AXI-Lite CSR request; only address bits [3:0] are decoded.
`axil_resp_o`	output	`axil_resp_t`	AXI-Lite CSR response.
`ct_src_i`	input	`logic`	Core-side cross-trigger pulse to transmit, synchronous to clk_i.
`ct_dst_o`	output	`logic`	Core-side received cross-trigger pulse, registered.
`busy_o`	output	`logic`	High while the stretched pulse is active in wire-OR mode, or while the outgoing or incoming handshake is active in point-to-point mode. Optional; leave unconnected when unused.
`ct_req_out_dout_en_o`	output	`logic`	Output enable for the CT_Req_out pad. Follows the stretched outgoing pulse in wire-OR mode; high in point-to-point mode.
`ct_req_out_din_en_o`	output	`logic`	Input enable for the CT_Req_out pad. High in wire-OR mode; low in point-to-point mode.
`ct_req_out_dout_o`	output	`logic`	Output data for the CT_Req_out pad. Carries the outgoing handshake request in point-to-point mode. Held low in wire-OR mode, or high when the CSR INVERT field is set.
`ct_req_out_din_i`	input	`logic`	Input data from the CT_Req_out pad. In wire-OR mode its synchronized assertion edge, falling unless inverted, pulses ct_dst_o; unused in point-to-point mode.
`ct_req_in_din_en_o`	output	`logic`	Input enable for the CT_Req_in pad. High in point-to-point mode; low in wire-OR mode.
`ct_req_in_din_i`	input	`logic`	Input data from the CT_Req_in pad. In point-to-point mode its synchronized request pulses ct_dst_o; unused in wire-OR mode.
`ct_ack_in_din_en_o`	output	`logic`	Input enable for the CT_Ack_in pad. High in point-to-point mode; low in wire-OR mode.
`ct_ack_in_din_i`	input	`logic`	Input data from the CT_Ack_in pad. In point-to-point mode its synchronized acknowledge clears the outgoing request; unused in wire-OR mode.
`ct_ack_out_dout_en_o`	output	`logic`	Output enable for the CT_Ack_out pad. High in point-to-point mode; low in wire-OR mode.
`ct_ack_out_dout_o`	output	`logic`	Output data for the CT_Ack_out pad. Acknowledges the synchronized CT_Req_in request in point-to-point mode; held low in wire-OR mode.