ctp_edge_detector

Detect rising edges on an already-synchronized CTP request.

Uses prim_edge_detector with EnSync disabled because signal_i is pre-synchronized; the primitive registers the previous level and derives the edge pulse combinationally from signal_i.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low asynchronous reset; clears the stored previous level.
`signal_i`	input	`logic`	Level to edge-detect, already synchronized to clk_i and polarity-corrected (the CT_Req_in pad input in the port core).
`posedge_pulse_o`	output	`logic`	One-cycle pulse on each rising edge of signal_i, combinational from signal_i; not consumed in cross_trigger_port_core.