ctp_pulse_stretcher

Stretch a core-side pulse to stretch_mult_i+1 clk_i cycles for wire-OR mode.

pulse_i is synchronous to clk_i; a new pulse while stretching restarts the counter so every chiplet still sees the event. stretched_pulse_o is the registered stretched pulse.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low asynchronous reset; clears the counter and the output.
`pulse_i`	input	`logic`	Outgoing core-side cross-trigger pulse, synchronous to clk_i; each assertion reloads the stretch counter.
`stretch_mult_i`	input	`logic [15:0]`	Stretch length: the output stays high for stretch_mult_i+1 clk_i cycles after the most recent pulse_i.
`stretched_pulse_o`	output	`logic`	Stretched pulse, registered and reset low; drives the CT_Req_out output enable in wire-OR mode.