ctp_synchronizer

Synchronize asynchronous CTP GPIO inputs into the core clock domain.

Double-synchronizes ct_req_out_din_i (wire-OR), ct_req_in_din_i, and ct_ack_in_din_i (point-to-point). Each input passes through a prim_flop_2sync that resets low.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset; clears every synchronizer stage.
`ct_req_out_din_i`	input	`logic`	Asynchronous CT_Req_out pad input, used in wire-OR mode.
`ct_req_in_din_i`	input	`logic`	Asynchronous CT_Req_in pad input, used in point-to-point mode.
`ct_ack_in_din_i`	input	`logic`	Asynchronous CT_Ack_in pad input, used in point-to-point mode.
`ct_req_out_din_sync_o`	output	`logic`	ct_req_out_din_i after two clk_i flops, without polarity correction.
`ct_req_in_din_sync_o`	output	`logic`	ct_req_in_din_i after two clk_i flops, without polarity correction.
`ct_ack_in_din_sync_o`	output	`logic`	ct_ack_in_din_i after two clk_i flops, without polarity correction.