drbg

Wrap CSRNG, EDN, and the wrapper-local seed and AXIS adapters into one DRBG block.

Integrate the CSRNG seed adapter, EDN endpoint AXI-Stream adapters, and separate CSRNG and EDN 64-bit AXI-Lite control ports. Register-bridge faults are sticky per path and held until each path's own clear.

The producer-driven entropy_stream_* input feeds the seed packer directly. The entropy source is fire-and-forget, and words offered while the seed path is full are dropped without forming a partial seed.

Native EDN endpoints bypass the AXI-Stream adapter; port width is 1 when EDN_NATIVE_ENDPOINT_COUNT is 0.

All wrapper logic stays in the single clk_i / rst_ni domain. Reset may assert asynchronously but must deassert synchronously to clk_i. The wrapper adds no internal reset-domain crossings or autonomous CSR control sequencing.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`SEED_FIFO_DEPTH`	`int unsigned`	`DrbgDefaultSeedFifoDepth`	Number of complete packed seeds queued for CSRNG. Must be at least 1.
`EDN_ENDPOINT_COUNT`	`int unsigned`	`DrbgDefaultEdnEndpointCount`	Number of EDN endpoints exposed as AXI-Stream outputs. Each output carries an independent random-data stream. Must be at least 1.
`EDN_NATIVE_ENDPOINT_COUNT`	`int unsigned`	`DrbgDefaultEdnNativeEndpointCount`	Number of native EDN req/rsp endpoints. Each exposes a raw edn_pkg bundle that bypasses the AXI-Stream FIFOs.
`EdnNativePortWidth`	`int unsigned`	`(EDN_NATIVE_ENDPOINT_COUNT == 0) ? 1 : EDN_NATIVE_ENDPOINT_COUNT`	Width of the native EDN ports, which is 1 when EDN_NATIVE_ENDPOINT_COUNT is 0. The single slot is then unused and its request should be tied off.
`ENDPOINT_FIFO_DEPTH`	`int unsigned`	`DrbgDefaultEndpointFifoDepth`	Depth of the FIFO on each AXI-Stream EDN endpoint. Must be at least 1.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low. May assert asynchronously; must deassert synchronously to clk_i.
`entropy_stream_data_i`	input	`logic [31:0]`	Producer entropy word into the seed packer.
`entropy_stream_vld_i`	input	`logic`	Producer entropy valid, with no back-pressure; a word offered while the packer holds a complete seed is dropped.
`edn_axis_o`	output	`drbg_axis_req_t [EDN_ENDPOINT_COUNT-1:0]`	EDN AXI-Stream requests toward consumers; tuser carries the EDN FIPS bit of each word.
`edn_axis_i`	input	`drbg_axis_rsp_t [EDN_ENDPOINT_COUNT-1:0]`	EDN AXI-Stream ready from consumers.
`edn_native_req_i`	input	`edn_pkg::edn_req_t [EdnNativePortWidth-1:0]`	Native EDN client requests (bypass AXI-Stream). Port width is 1 when EDN_NATIVE_ENDPOINT_COUNT is 0.
`edn_native_rsp_o`	output	`edn_pkg::edn_rsp_t [EdnNativePortWidth-1:0]`	Native EDN client responses.
`csrng_axil_req_i`	input	`csrng_axil_req_t`	CSRNG AXI-Lite CSR request.
`csrng_axil_rsp_o`	output	`csrng_axil_rsp_t`	CSRNG AXI-Lite CSR response.
`edn_axil_req_i`	input	`edn_axil_req_t`	EDN AXI-Lite CSR request.
`edn_axil_rsp_o`	output	`edn_axil_rsp_t`	EDN AXI-Lite CSR response.
`otp_en_csrng_sw_app_read_i`	input	`prim_mubi_pkg::mubi8_t`	OTP enable for CSRNG SW app read.
`lc_hw_debug_en_i`	input	`lc_ctrl_pkg::lc_tx_t`	Lifecycle HW-debug enable.
`csrng_alert_rx_i`	input	`prim_alert_pkg::alert_rx_t [csrng_reg_pkg::NumAlerts-1:0]`	CSRNG alert receivers.
`csrng_alert_tx_o`	output	`prim_alert_pkg::alert_tx_t [csrng_reg_pkg::NumAlerts-1:0]`	CSRNG alert transmitters.
`edn_alert_rx_i`	input	`prim_alert_pkg::alert_rx_t [edn_reg_pkg::NumAlerts-1:0]`	EDN alert receivers.
`edn_alert_tx_o`	output	`prim_alert_pkg::alert_tx_t [edn_reg_pkg::NumAlerts-1:0]`	EDN alert transmitters.
`intr_cs_cmd_req_done_o`	output	`logic`	CSRNG cmd-req-done interrupt.
`intr_cs_entropy_req_o`	output	`logic`	CSRNG entropy-req interrupt.
`intr_cs_hw_inst_exc_o`	output	`logic`	CSRNG HW-instance exception interrupt.
`intr_cs_fatal_err_o`	output	`logic`	CSRNG fatal-error interrupt.
`intr_edn_cmd_req_done_o`	output	`logic`	EDN cmd-req-done interrupt.
`intr_edn_fatal_err_o`	output	`logic`	EDN fatal-error interrupt.
`csrng_bus_err_o`	output	`logic`	Sticky CSRNG register-bridge fault, set when a TL-UL response from CSRNG carries d_error. Held until csrng_bus_err_clr_i.
`csrng_bus_err_clr_i`	input	`logic`	Clear the CSRNG bus-fault sticky, active-high; a fault in the same cycle still sets it.
`edn_bus_err_o`	output	`logic`	Sticky EDN register-bridge fault, set when a TL-UL response from EDN carries d_error. Held until edn_bus_err_clr_i.
`edn_bus_err_clr_i`	input	`logic`	Clear the EDN bus-fault sticky, active-high; a fault in the same cycle still sets it.