drbg_axil64_lane_adapter

Filter 64-bit AXI-Lite traffic down to aligned single-lane 32-bit accesses.

Forwards supported beats into the existing 32-bit AXI-Lite to TL-UL bridge, one transaction at a time; a read accepted in the same cycle as a write is served first, and no read is accepted while write address or data is held. A read must be 4-byte aligned and returns the addressed 32-bit lane with the other lane zero; a write must be 4-byte aligned with WSTRB exactly 0x0F for the lower lane or 0xF0 for the upper lane, selected by address bit 2. Unsupported accesses return AXI SLVERR and emit no downstream request.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Async reset, active-low.
`axil64_req_i`	input	`axil64_req_t`	64-bit AXI-Lite request in.
`axil64_rsp_o`	output	`axil64_rsp_t`	64-bit AXI-Lite response out.
`axil32_req_o`	output	`axil32_req_t`	Forwarded 32-bit AXI-Lite request.
`axil32_rsp_i`	input	`axil32_rsp_t`	32-bit AXI-Lite response from the bridge.
`unsupported_access_pulse_o`	output	`logic`	One-cycle pulse when an unsupported access is rejected with SLVERR; a SLVERR returned by the bridge does not pulse it.
`forwarded_read_pulse_o`	output	`logic`	Pulse when a read is forwarded.
`forwarded_write_pulse_o`	output	`logic`	Pulse when a write is forwarded.