efuse_interface_shim

Turn fuse-command requests into foundry APB accesses for an example fuse-bank model.

Hosts SHIM CSRs on fuse_bank_ctrl_*. Sequences fuse_command_req_i onto efuse_model_otp_* APB, waiting the programmed bank init time before each command; debug_bus_o exposes shim state. The APB macro interface is foundry-specific in real integrations.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`SHADOW_REG_BITS`	`int unsigned`	`24576`	Fuse array size in bits; declared but not used in this module.
`CounterWidth`	`int unsigned`	`32`	Width of the read and write bank init-time counters.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low asynchronous reset.
`fuse_bank_ctrl_req_i`	input	`efuse_axil_req_t`	AXI4-Lite request to the fuse bank control registers; only address bits [2:0] are decoded.
`fuse_bank_ctrl_resp_o`	output	`efuse_axil_resp_t`	AXI4-Lite response from the fuse bank control registers, which hold the bank init time.
`fuse_command_req_i`	input	`fuse_command_req_t`	Filtered fuse command from the interface controller: read, program, or program with read-back.
`fuse_command_resp_o`	output	`fuse_command_resp_t`	Fuse command response, one valid pulse per word read or per program.
`efuse_model_otp_req_o`	output	`efuse_apb_req_t`	Registered APB request to the fuse bank model, byte addressed; a program writes one bit with one byte strobe.
`efuse_model_otp_resp_i`	input	`efuse_apb_resp_t`	APB response from the fuse bank model.
`debug_bus_o`	output	`logic [15:0]`	Shim status: {3'b0, write counter error, write FSM state, 3'b0, read counter error, read FSM state}.