efuse_program_interface

Program one fuse bit through the fuse-command interface with optional read-back and timeouts.

program_go_i starts a program to program_addr_i with program_data_in_i; program_read_back_enable_i requests post-program read-back. program_addr_oob_i is computed upstream against the full-width CSR field because casting to efuse_addr_t truncates upper bits. Honors secure_tm_blocked_i, efuse_req_err_i, and optional program_req_timeout_* ; sticky address errors clear with program_addr_error_clear_i. is_programing_o and program_target_addr_o feed the guard while a program is active.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`EFUSE_WORD_WIDTH`	`unsigned`	`32`	Program/read data word width; declared but not used in this module.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low asynchronous reset.
`test_en_i`	input	`logic`	DFT test enable; not used in this module.
`program_enable_i`	input	`logic`	Program operations allowed; a start while low completes immediately with an error.
`is_programing_o`	output	`logic`	High while a program command is outstanding, for the guard.
`program_target_addr_o`	output	`efuse_addr_t`	Fuse bit address of the outstanding program command; zero when idle.
`program_addr_i`	input	`efuse_addr_t`	Fuse bit address to program, sampled on a start.
`program_data_in_i`	input	`logic`	Bit value to program; a start with zero is rejected with an error.
`program_go_i`	input	`logic`	Starts a program operation when high in the idle state.
`program_read_back_enable_i`	input	`logic`	Selects the program-with-read-back command, which returns the programmed word.
`program_busy_o`	output	`logic`	High while a program operation waits for its response.
`program_done_o`	output	`logic`	Set when the last program operation completed; cleared by the next start.
`program_error_o`	output	`logic`	Set when the last program operation failed: rejected, blocked, errored by the bank, or timed out.
`program_read_back_data_o`	output	`efuse_data_t`	Data word returned with the last successful program response.
`program_addr_oob_i`	input	`logic`	High when the full-width CSR program address is beyond the fuse array; a start is then rejected.
`program_addr_error_o`	output	`logic`	Sticky out-of-bounds program address error.
`program_addr_error_clear_i`	input	`logic`	Clears the sticky address error; a same-cycle new error takes priority.
`efuse_req_err_i`	input	`logic`	Guard lock error; ends an outstanding program with an error.
`secure_tm_blocked_i`	input	`logic`	Guard secure-test-mode block; ends an outstanding program with an error.
`program_req_timeout_en_i`	input	`logic`	Enables the response timeout for program operations.
`program_req_timeout_cycles_i`	input	`logic [27:0]`	Response timeout in clock cycles.
`fuse_command_req_o`	output	`fuse_command_req_t`	Program command to the guard; valid only while waiting for the response.
`fuse_command_resp_i`	input	`fuse_command_resp_t`	Filtered response to the program command.
`is_program_timeout_debug_o`	output	`logic`	One-cycle pulse when a program operation times out.