entropy_debug_monitor

Select one of NSIGNALS inputs and optionally divide it for an off-chip debug observe pin.

select_signal_i chooses the bit; select_freq_div_i selects a power-of-two divider from 2^0 through 2^(FREQ_DIV_WIDTH-1). sig_monitor_o is the divided observable.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NSIGNALS`	`int unsigned`	`32`	Selectable monitor input count.
`FREQ_DIV_WIDTH`	`int unsigned`	`8`	Divider tap count including the undivided signal; the ripple divider has FREQ_DIV_WIDTH-1 stages.

Ports

Table 2. Ports
Name	Direction	Type	Description
`rst_ni`	input	`logic`	Active-low asynchronous reset of the ripple divider.
`select_signal_i`	input	`logic [$clog2(NSIGNALS)-1:0]`	Binary index of the signal_i bit to observe.
`signal_i`	input	`logic [NSIGNALS-1:0]`	Candidate observe signals; bit select_signal_i clocks the ripple divider.
`select_freq_div_i`	input	`logic [$clog2(FREQ_DIV_WIDTH-1)-1:0]`	Divider tap index; value k observes the selected signal divided by 2^k.
`sig_monitor_o`	output	`logic`	Selected signal after the chosen power-of-two divider, for an off-chip observe pin.