entropy_ripple_divider
Divide an input clock through cascaded asynchronous toggle flip-flops.
Each stage divides by two; div_o[0] is clk_i, div_o[1] is clk_i/2, through div_o[NUM_STAGES] = clk_i/2^NUM_STAGES. Stages use resettable D flops with inverted Q fed to D; the first stage clocks from clk_i and later stages from the prior Q.
This asynchronous design intentionally violates synchronous rules and is only for sampler frequency division where those constraints are not critical.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
NUM_STAGES | int unsigned | 7 | Number of divide-by-2 stages. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
rst_ni | input | logic | Active-low asynchronous reset; clears every divider stage. |
clk_i | input | logic | Clock to divide. |
div_o | output | logic [NUM_STAGES:0] | Divided outputs [0]=clk_i, [1]=÷2, [2]=÷4, etc. |