entropy_sampler_clocks

Mux and ripple-divide per-lane sample clocks for NRINGS noise generators.

Each generator selects external sample_clk_i or a shared internal ring oscillator, then divides by powers of two from ÷1 through ÷32.

The shared RO enables when any generator enables and detunes when any generator requests detune (OR aggregation); detune selects its full 109-stage path and otherwise it runs on its 53-stage tap. It is about 10× longer than the noise ROs to hit the target frequency ratio.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NRINGS`	`int unsigned`	`12`	Ring-oscillator lane count.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock; not used in this module.
`rst_ni`	input	`logic`	Active-low asynchronous reset of the ripple dividers.
`sample_clk_i`	input	`logic`	External sample clock for lanes whose sample_clk_select_i bit is low.
`sample_clk_select_i`	input	`logic [NRINGS-1:0]`	Per-lane clock source: high for the shared ring oscillator, low for sample_clk_i; change only while that lane's enable_i is low.
`enable_i`	input	`logic [NRINGS-1:0]`	Per-lane enable requests; any set bit starts the shared ring oscillator.
`detune_ro_i`	input	`logic [NRINGS-1:0]`	Detune requests for the shared ring oscillator; any set bit selects its full-length feedback path.
`sample_clk_divide_i`	input	`logic [NRINGS-1:0][4:0]`	Per-lane divide exponent: 0-5 divide by 1 to 32, other values divide by 4; change only while that lane's enable_i is low.
`sample_clk_o`	output	`logic [NRINGS-1:0]`	Per-lane selected and divided sample clock for the noise-source sampling flop.