entropy_source
Generate conditioned entropy from a ring-oscillator array with health tests and AXI-Lite control.
A 12-lane array of ring oscillators of differing lengths, with metastable sampling, feeds a GF(2^8) extractor whose 32-bit stream runs online Repetition, Adaptive Proportion, and Markov health tests and an optional SHA-256 whitener. rosc_sample_clk_i is the external sample clock.
Interfaces:
- The AXI-Lite slave carries register-based configuration and data access.
- signal_monitor_o observes intermediate signals.
- irq_o aggregates sticky fault and health status for the SEP host.
Boot-time validation uses the main_sm gate: entropy reaches the whitener, the main FIFO and the extracted-stream observe FIFO only after CTRL.MODULE_ENABLE is set and a boot health-test window passes, and new entropy stops entering when MODULE_ENABLE clears or the alert threshold trips.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | logic | System clock. |
rst_ni | input | logic | Active-low asynchronous reset. |
s_axil_awvalid_i | input | logic | AXI-Lite write-address valid. |
s_axil_awready_o | output | logic | AXI-Lite write-address ready. |
s_axil_awaddr_i | input | logic [8:0] | AXI-Lite write byte address within the register map. |
s_axil_awprot_i | input | logic [2:0] | AXI-Lite write protection attributes. |
s_axil_wvalid_i | input | logic | AXI-Lite write-data valid. |
s_axil_wready_o | output | logic | AXI-Lite write-data ready. |
s_axil_wdata_i | input | logic [31:0] | AXI-Lite write data. |
s_axil_wstrb_i | input | logic [3:0] | AXI-Lite write byte strobes. |
s_axil_bvalid_o | output | logic | AXI-Lite write-response valid. |
s_axil_bready_i | input | logic | AXI-Lite write-response ready. |
s_axil_bresp_o | output | logic [1:0] | AXI-Lite write response code. |
s_axil_arvalid_i | input | logic | AXI-Lite read-address valid. |
s_axil_arready_o | output | logic | AXI-Lite read-address ready. |
s_axil_araddr_i | input | logic [8:0] | AXI-Lite read byte address within the register map. |
s_axil_arprot_i | input | logic [2:0] | AXI-Lite read protection attributes. |
s_axil_rvalid_o | output | logic | AXI-Lite read-data valid. |
s_axil_rready_i | input | logic | AXI-Lite read-data ready. |
s_axil_rdata_o | output | logic [31:0] | AXI-Lite read data. |
s_axil_rresp_o | output | logic [1:0] | AXI-Lite read response code. |
signal_monitor_o | output | logic | Debug observe signal chosen and divided by DEBUG_CTRL. |
rosc_sample_clk_i | input | logic | External ring-oscillator sample clock, asynchronous to clk_i. |
entropy_stream_data_o | output | logic [31:0] | Word offered to the main entropy FIFO: whitener output, which is the extracted stream itself while whitening is disabled, or packed lane bytes when the compressor is bypassed. |
entropy_stream_vld_o | output | logic | Qualifies entropy_stream_data_o; independent of FIFO_CTRL.ENABLE. |
irq_o | output | logic | Level interrupt: OR of the INTR_STATUS sticky bits masked by INTR_ENABLE. |