gpio_shim

Shim a GPIO pad with 2nd-HW override, LSIO, strap capture, and model control.

force_primary_i preempts hw2 override back to the primary plane (for example CAT-THERM over a 2nd-HW-function override). External drive, pull, and glitch-filter controls can override register settings when selected: the electrical controls come, in priority order, from the cold-reset defaults, the LSIO pin select, CONTROL.config_enable, then the LSIO software select. AXI-Lite addresses below the GPIO_CTRL base plus size reach the gpio_ctrl register block; the base-plus-size address and above receive DECERR from an error subordinate. Addresses below the base are decoded away upstream, so this shim bounds only the top of the aperture. While rst_cold_ni is low a latch follows the pad input, and it holds the strap value once rst_cold_ni rises.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`INPUT_BY_DEFAULT`	`bit`	`1'b1`	Enables strap capture and drives CONTROL.strap_valid; when clear, captured_strap_o is tied low.
`ENABLE_PULL`	`bit`	`1'b0`	Pull enable driven in cold reset and when no source owns the electrical controls.
`USE_PULL_UP`	`bit`	`1'b0`	Pull select driven in cold reset and when no source owns the electrical controls; 1 selects pull-up.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_primary_ni`	input	`logic`	Primary async reset, active-low; resets the demux, error subordinate and register block.
`rst_cold_ni`	input	`logic`	Cold reset, active-low; forces the default electrical controls and opens the strap latch while low.
`test_en_i`	input	`logic`	DFT test enable, driven to the demux test input.
`core2pad_i`	input		Primary core-to-pad data.
`core2pad_en_i`	input		Primary core-to-pad enable.
`pad2core_o`	output		Pad input to the primary plane, driven from gpio_in_i whether or not the override is active.
`pad2core_en_i`	input		Primary pad-to-core enable.
`core2pad_ovrd_i`	input	`logic`	2nd-HW core-to-pad data, used while CONTROL.hw2_ovrd is set and force_primary_i is low.
`core2pad_en_ovrd_i`	input	`logic`	2nd-HW core-to-pad enable.
`pad2core_ovrd_o`	output	`logic`	2nd-HW pad-to-core data; low while the override is inactive.
`pad2core_en_ovrd_i`	input	`logic`	2nd-HW pad-to-core enable.
`force_primary_i`	input	`logic`	Force the primary plane over hw2 override. Assert for safety preempt (e.g. CAT-THERM).
`ext_intf_sel_i`	input	`logic`	LSIO pin select; the ext_* controls take priority over the register settings unless reg_lsio_disable_i is set.
`reg_lsio_sel_i`	input	`logic`	Software LSIO select; applies the ext_* controls only when CONTROL.config_enable is clear.
`reg_lsio_disable_i`	input	`logic`	Register LSIO disable; blocks both LSIO selects.
`ext_drive_strength_i`	input	`logic [2:0]`	External drive strength.
`ext_pull_en_i`	input	`logic`	External pull enable.
`ext_pull_sel_i`	input	`logic`	External pull select.
`ext_gf_disable_i`	input	`logic`	Disable the glitch filter.
`captured_strap_o`	output	`logic`	Pad input latched while rst_cold_ni is low; also read back as CONTROL.strap_value.
`gpio_in_i`	input	`logic`	Pad input level.
`gpio_out_o`	output	`logic`	Pad output data.
`gpio_in_en_o`	output	`logic`	Pad input enable.
`gpio_out_en_o`	output	`logic`	Pad output enable.
`gpio_ctrl_o`	output	`gpio_model_ctrl_t`	Pad drive strength, pull and glitch-filter controls; sps is always low.
`gpio_status_i`	input	`gpio_model_status_t`	Model status struct; unused.
`axil_req_i`	input	`gpio_axil_req_t`	AXI-Lite CSR request.
`axil_resp_o`	output	`gpio_axil_resp_t`	AXI-Lite CSR response.