i2c_bus_monitor

Monitor SCL and SDA for START/STOP, bus-free, and active/inactive timeouts.

The monitor runs while controller, multi-controller or target mode is enabled. A START or STOP is reported once SCL has stayed high for thd_dat_i cycles after the SDA edge. thd_dat_i is the data hold time (< 200 ns, < thd_sta). t_buf_i is the bus free time (< 5 us). bus_active_timeout_i covers SCL held low (~25 ms); bus_inactive_timeout_i covers SCL held high with SDA stable (~50 us), and zero disables it.

Ports

Table 1. Ports
NameDirectionTypeDescription
clk_iinputlogicSystem clock.
rst_niinputlogicAsync reset, active-low.
scl_iinputlogicSCL pad input.
sda_iinputlogicSDA pad input.
controller_enable_iinputlogicController mode enabled.
multi_controller_enable_iinputlogicMulti-controller mode enabled; the bus starts busy and bus_free_o is high only in the free state.
target_enable_iinputlogicTarget mode enabled.
target_idle_iinputlogicTarget FSM is idle; suppresses event_host_timeout_o.
thd_dat_iinputlogic [12:0]Data hold time in clocks (< 200 ns, < thd_sta); also the START and STOP qualification delay.
t_buf_iinputlogic [12:0]Bus free time in clocks (< 5 us), counted after a STOP.
bus_active_timeout_iinputlogic [29:0]SCL-low timeout threshold in clocks (~25 ms).
bus_active_timeout_en_iinputlogicEnable SCL-low timeout.
bus_inactive_timeout_iinputlogic [30:0]SCL-high timeout threshold in clocks (~50 us); zero disables it.
bus_free_ooutputlogicBus free for a new transfer; outside multi-controller mode low only during the t_buf_i wait after a STOP.
start_detect_ooutputlogicOne-cycle pulse on a qualified START or repeated START.
stop_detect_ooutputlogicOne-cycle pulse on a qualified STOP.
event_bus_active_timeout_ooutputlogicOne-cycle pulse when SCL is held low past the threshold while bus_active_timeout_en_i is set.
event_host_timeout_ooutputlogicPulse when SCL is held high past the threshold while the target is not idle.