i2c_controller_fsm

Drive the I2C controller FSM from the FMT FIFO onto SCL and SDA.

Issues START and STOP around fmt_byte_i per FMT flags, waits while the target stretches SCL, and reports NAK, arbitration-loss, and stretch-timeout events.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`CONTROLLER_TX_FIFO_DEPTH`	`int unsigned`	`64`	FMT FIFO depth.
`ControllerTxFifoDepthWidth`	`int unsigned`	`$clog2(CONTROLLER_TX_FIFO_DEPTH + 1)`	clog2(depth+1) for FMT fill.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Async reset, active-low.
`scl_i`	input	`logic`	SCL pad input.
`scl_o`	output	`logic`	SCL pad output.
`sda_i`	input	`logic`	SDA pad input.
`sda_o`	output	`logic`	SDA pad output.
`bus_free_i`	input	`logic`	Bus free for a new transfer.
`transmitting_o`	output	`logic`	Controller is driving SDA.
`host_enable_i`	input	`logic`	Host/controller enable.
`halt_controller_i`	input	`logic`	Halt the controller FSM in IDLE.
`fmt_fifo_rvalid_i`	input	`logic`	FMT FIFO has valid data.
`fmt_fifo_depth_i`	input	`logic [ControllerTxFifoDepthWidth-1:0]`	FMT FIFO fill level.
`fmt_fifo_rready_o`	output	`logic`	Pop FMT FIFO.
`fmt_byte_i`	input	`logic [7:0]`	Byte in FMT FIFO to send to the target.
`fmt_flag_start_before_i`	input	`logic`	Issue START before sending the byte.
`fmt_flag_stop_after_i`	input	`logic`	Issue STOP after sending the byte.
`fmt_flag_read_bytes_i`	input	`logic`	Byte is a number of reads; zero means 256.
`fmt_flag_read_continue_i`	input	`logic`	Host sends Ack to the final read byte.
`fmt_flag_nak_ok_i`	input	`logic`	No ACK is expected.
`unhandled_unexp_nak_i`	input	`logic`	Unexpected-NACK IRQ still pending.
`unhandled_nak_timeout_i`	input	`logic`	NACK-handler timeout event not cleared.
`rx_fifo_wvalid_o`	output	`logic`	Push a read byte into the RX FIFO.
`rx_fifo_wdata_o`	output	`logic [CONTROLLER_RX_FIFO_WIDTH-1:0]`	Byte read from the target for the RX FIFO.
`host_idle_o`	output	`logic`	Host is idle.
`thigh_i`	input	`logic [12:0]`	SCL high period in clock units.
`tlow_i`	input	`logic [12:0]`	SCL low period in clock units.
`t_r_i`	input	`logic [12:0]`	Rise time of SDA and SCL in clock units.
`t_f_i`	input	`logic [12:0]`	Fall time of SDA and SCL in clock units.
`thd_sta_i`	input	`logic [12:0]`	Hold time for (repeated) START in clock units.
`tsu_sta_i`	input	`logic [12:0]`	Setup time for repeated START in clock units.
`tsu_sto_i`	input	`logic [12:0]`	Setup time for STOP in clock units.
`thd_dat_i`	input	`logic [12:0]`	Data hold time in clock units.
`sda_interference_i`	input	`logic`	SCL high and SDA does not match while transmitting.
`bus_timeout_i`	input	`logic`	SCL held low past the bus timeout.
`stretch_timeout_i`	input	`logic [29:0]`	Max clocks a target may stretch the clock.
`timeout_enable_i`	input	`logic`	Enables event_stretch_timeout_o.
`host_nack_handler_timeout_i`	input	`logic [30:0]`	Clocks the FSM may stay halted on an unhandled Host-Mode NACK before it issues a STOP.
`host_nack_handler_timeout_en_i`	input	`logic`	Enable unhandled-NACK timeout.
`event_nak_o`	output	`logic`	Target did not Ack when expected.
`event_unhandled_nak_timeout_o`	output	`logic`	SW did not handle the NACK in time; held while the FSM stays halted.
`event_arbitration_lost_o`	output	`logic`	SDA unstable, SDA interference, or a failed START or STOP symbol.
`event_scl_interference_o`	output	`logic`	Other device forcing SCL low.
`event_stretch_timeout_o`	output	`logic`	Target stretches clock past max time.
`event_sda_unstable_o`	output	`logic`	SDA is not constant during an SCL pulse.
`event_cmd_complete_o`	output	`logic`	Command is complete.