i2c_core

Bind I2C register outs to the controller, target, and bus-monitor FSMs.

Exposes SMBus sideband, DMA ready levels, a combined irq_o, and a four-bit debug bus. SCL and SDA outputs are registered; the SCL, SDA, SMBus SUS and SMBus ALERT inputs are synchronized to clk_i. debug_o[0] is SDA and [1] is SCL, each sampled once by clk_i, [2] is target_idle, and [3] is the unextended OR of the controller error events.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`CONTROLLER_TX_FIFO_DEPTH`	`int unsigned`	`64`	Entries in the controller format (FMT) FIFO; 1 to 4095.
`CONTROLLER_RX_FIFO_DEPTH`	`int unsigned`	`64`	Entries in the controller receive (RX) FIFO; 1 to 4095.
`TARGET_TX_FIFO_DEPTH`	`int unsigned`	`64`	Entries in the target transmit (TX) FIFO; 1 to 4095.
`TARGET_RX_FIFO_DEPTH`	`int unsigned`	`268`	Entries in the target acquisition (ACQ) FIFO; 1 to 4095.
`INPUT_DELAY_CYCLES`	`int unsigned`	`0`	External SCL/SDA input delay in clk_i cycles; lengthens the interference-detection blanking window after each output change.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input		System clock.
`rst_ni`	input		Async reset, active-low.
`reg_out_i`	input	`i2c_reg_pkg::i2c__out_t`	Register-block outputs into the core.
`reg_in_o`	output	`i2c_reg_pkg::i2c__in_t`	Register-block inputs from the core.
`scl_i`	input		SCL pad input, synchronized to clk_i by a two-flop synchronizer.
`scl_o`	output	`logic`	SCL pad output, registered AND of the controller and target FSM drives, or OVRD.SCLVAL under OVRD.TXOVRDEN; 0 pulls the line low, 1 releases it.
`sda_i`	input		SDA pad input, synchronized to clk_i by a two-flop synchronizer.
`sda_o`	output	`logic`	SDA pad output, registered AND of the controller and target FSM drives, or OVRD.SDAVAL under OVRD.TXOVRDEN; 0 pulls the line low, 1 releases it.
`smbus_en_i`	input	`logic`	When low, masks smbalert_ni so SMBus ALERT reads as deasserted.
`smbsus_ni`	input	`logic`	SMBus SUS pin in, active-low; synchronized and reported in SMBUS_STATUS.
`smbsus_no`	output	`logic`	SMBus SUS pin out, active-low; driven from SMBUS_CTRL.SMBSUS in host mode without line loopback, high otherwise.
`smbalert_ni`	input	`logic`	SMBus ALERT pin in, active-low; synchronized, reported in SMBUS_STATUS and raises the SMBALERT interrupt.
`smbalert_no`	output	`logic`	SMBus ALERT pin out, active-low; driven from SMBUS_CTRL.SMBALERT in target mode without loopback, high otherwise.
`controller_tx_ready_o`	output	`logic`	Controller TX DMA ready; drops when the FMT FIFO fills and returns once its level falls below the FMT threshold.
`controller_rx_ready_o`	output	`logic`	Controller RX DMA ready; rises when the RX level exceeds the RX threshold and stays high until the FIFO empties.
`target_tx_ready_o`	output	`logic`	Target TX DMA ready; drops when the TX FIFO fills and returns once its level falls below the TX threshold.
`target_rx_ready_o`	output	`logic`	Target RX DMA ready; rises when the ACQ level exceeds the ACQ threshold and stays high until the FIFO empties.
`irq_o`	output	`logic`	Level interrupt; OR of the INTR_STATE sources masked by INTR_ENABLE.
`debug_o`	output	`logic [3:0]`	[0] SDA and [1] SCL, each sampled once by clk_i; [2] target_idle; [3] OR of the NACK, arbitration-lost, interference, timeout and SDA-unstable controller events, not stretched.