i2c_target_fsm

Answer matched I2C addresses in the target FSM and fill the ACQ FIFO.

Drives SCL stretch for TX underrun, a nearly full ACQ FIFO and ACK-control mode, applies address masks, and pulses events for match, NACK, unexpected STOP, and arbitration loss.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`TARGET_RX_FIFO_DEPTH`	`int unsigned`	`64`	ACQ FIFO depth.
`TargetRxFifoDepthWidth`	`int unsigned`	`$clog2(TARGET_RX_FIFO_DEPTH+1)`	clog2(depth+1) for ACQ fill.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Async reset, active-low.
`scl_i`	input	`logic`	Serial clock input from the I2C bus.
`scl_o`	output	`logic`	Serial clock output to the I2C bus.
`sda_i`	input	`logic`	Serial data input from the I2C bus.
`sda_o`	output	`logic`	Serial data output to the I2C bus.
`start_detect_i`	input	`logic`	START from the bus monitor.
`stop_detect_i`	input	`logic`	STOP from the bus monitor.
`transmitting_o`	output	`logic`	Target is transmitting SDA (disambiguates high sda_o).
`target_enable_i`	input	`logic`	Enable target functionality.
`tx_fifo_rvalid_i`	input	`logic`	TX FIFO has valid data.
`tx_fifo_rready_o`	output	`logic`	Pop entry from TX FIFO.
`tx_fifo_rdata_i`	input	`logic [TARGET_TX_FIFO_WIDTH-1:0]`	Byte in TX FIFO to send to the host.
`acq_fifo_wvalid_o`	output	`logic`	Push valid data into the ACQ FIFO.
`acq_fifo_wdata_o`	output	`logic [TARGET_RX_FIFO_WIDTH-1:0]`	Data to write to the ACQ FIFO.
`acq_fifo_depth_i`	input	`logic [TargetRxFifoDepthWidth-1:0]`	Fill level of the ACQ FIFO.
`acq_fifo_full_o`	output	`logic`	High while two or fewer ACQ FIFO entries are free.
`acq_fifo_rdata_i`	input	`logic [TARGET_RX_FIFO_WIDTH-1:0]`	ACQ peek used only for assertions.
`target_idle_o`	output	`logic`	Target is idle.
`t_r_i`	input	`logic [12:0]`	Rise time of SDA and SCL in clock units.
`tsu_dat_i`	input	`logic [12:0]`	Data setup time in clock units.
`thd_dat_i`	input	`logic [12:0]`	Data hold time in clock units.
`nack_timeout_i`	input	`logic [30:0]`	Max time the target may stretch until it should NACK.
`nack_timeout_en_i`	input	`logic`	Enable NACK timeout.
`nack_addr_after_timeout_i`	input	`logic`	NACK address after timeout.
`arbitration_lost_i`	input	`logic`	Lost arbitration while transmitting.
`bus_timeout_i`	input	`logic`	Bus timed out with SCL held low too long.
`unhandled_tx_stretch_event_i`	input	`logic`	Unhandled event requests TX stretching.
`ack_ctrl_mode_i`	input	`logic`	ACK Control Mode enabled.
`acq_start_stop_en_i`	input	`logic`	Enable START/STOP in the ACQ FIFO.
`auto_ack_cnt_i`	input	`logic [8:0]`	Current TARGET_ACK_CTRL.NBYTES counter value.
`auto_ack_cnt_clr_o`	output	`logic`	Clear the TARGET_ACK_CTRL.NBYTES counter.
`auto_ack_cnt_decr_o`	output	`logic`	Decrement the TARGET_ACK_CTRL.NBYTES counter.
`sw_nack_i`	input	`logic`	SW pulses high to NACK while stretching in ack_ctrl.
`ack_ctrl_stretching_o`	output	`logic`	Stretching due to zero Auto ACK count.
`acq_fifo_next_data_o`	output	`logic [7:0]`	Next data byte for SW NACK decisions.
`target_address0_i`	input	`logic [6:0]`	Address 0.
`target_mask0_i`	input	`logic [6:0]`	Address 0 mask; zero disables address 0.
`target_address1_i`	input	`logic [6:0]`	Address 1.
`target_mask1_i`	input	`logic [6:0]`	Address 1 mask; zero disables address 1.
`event_address_match_o`	output	`logic`	One of the target addresses matched.
`event_target_nack_o`	output	`logic`	This target sent a NACK.
`event_cmd_complete_o`	output	`logic`	Command is complete.
`event_tx_stretch_o`	output	`logic`	TX transaction is being stretched.
`event_unexp_stop_o`	output	`logic`	STOP during a read addressed to this target without a preceding host NACK.
`event_tx_arbitration_lost_o`	output	`logic`	Arbitration was lost during a read transfer.
`event_tx_bus_timeout_o`	output	`logic`	Bus timed out during a read transfer.
`event_read_cmd_received_o`	output	`logic`	A read awaits confirmation for TX FIFO release.