i2c_wrap

Demux one AXI-Lite slave onto NUM_I2CS I2C cores and a shared ctrl map.

NumRegMaps is NUM_I2CS plus one for ctrl and one for the error slave. Addresses outside every map reach the error slave, which answers DECERR with read data 0xBADCAB1E. The ctrl map holds one I2C_CTRL register per instance, which drives i2c_en_o, i2c_controller_mode_en_o and that instance's SMBus enable. SMBus, DMA ready, IRQ, and debug ports are vectors with one slice per instance. Each instance's debug nibble matches i2c_core's four-bit debug bus.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NUM_I2CS`	`int unsigned`	`3`	Number of I2C instances; 1 to i2c_wrap_pkg::MaxNumI2cs.
`CONTROLLER_TX_FIFO_DEPTH`	`int unsigned`	`64`	Entries in the controller format (FMT) FIFO in each instance; 1 to 4095.
`CONTROLLER_RX_FIFO_DEPTH`	`int unsigned`	`64`	Entries in the controller receive (RX) FIFO in each instance; 1 to 4095.
`TARGET_TX_FIFO_DEPTH`	`int unsigned`	`64`	Entries in the target transmit (TX) FIFO in each instance; 1 to 4095.
`TARGET_RX_FIFO_DEPTH`	`int unsigned`	`268`	Entries in the target acquisition (ACQ) FIFO in each instance; 1 to 4095.
`INPUT_DELAY_CYCLES`	`int unsigned`	`0`	External SCL/SDA input delay in clk_i cycles; lengthens the interference-detection blanking window after each output change.
`I2C_CTRL_REG_MAP_BASE_ADDR`	`bit [i2c_wrap_pkg::RegAddrWidth-1:0]`	`0`	Shared ctrl register-map base.
`I2C_CTRL_REG_MAP_SIZE`	`bit [i2c_wrap_pkg::RegAddrWidth-1:0]`	`0`	Shared ctrl register-map size.
`I2C_0__REG_MAP_BASE_ADDR`	`bit [i2c_wrap_pkg::RegAddrWidth-1:0]`	`0`	Instance 0 register-map base.
`I2C_0__REG_MAP_SIZE`	`bit [i2c_wrap_pkg::RegAddrWidth-1:0]`	`0`	Per-instance register-map size.
`I2C_INSTANCE_SPACING`	`bit [i2c_wrap_pkg::RegAddrWidth-1:0]`	`0`	Byte spacing between instances.
`NumRegMaps`	`int unsigned`	`NUM_I2CS + 2`	Decode targets: instances + ctrl + error slave.
`CtrlRegMap`	`i2c_wrap_reg_map_select_t`	`i2c_wrap_reg_map_select_t'(NumRegMaps - 2)`	Select index for the ctrl map.
`UndefinedRegMap`	`i2c_wrap_reg_map_select_t`	`i2c_wrap_reg_map_select_t'(NumRegMaps - 1)`	Select index for the error slave.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Async reset, active-low.
`axil_req_i`	input	`i2c_wrap_pkg::axil_req_t`	Shared AXI-Lite request.
`axil_resp_o`	output	`i2c_wrap_pkg::axil_resp_t`	Shared AXI-Lite response.
`i2c_en_o`	output	`logic [NUM_I2CS-1:0]`	Per-instance I2C_CTRL.I2C_EN value; not consumed by the I2C instance.
`i2c_controller_mode_en_o`	output	`logic [NUM_I2CS-1:0]`	Per-instance I2C_CTRL.I2C_CONTROLLER_MODE_EN value; not consumed by the I2C instance.
`scl_i`	input	`logic [NUM_I2CS-1:0]`	Per-instance SCL pad input, synchronized to clk_i inside each instance.
`scl_o`	output	`logic [NUM_I2CS-1:0]`	Per-instance SCL pad output; 0 pulls the line low, 1 releases it.
`sda_i`	input	`logic [NUM_I2CS-1:0]`	Per-instance SDA pad input, synchronized to clk_i inside each instance.
`sda_o`	output	`logic [NUM_I2CS-1:0]`	Per-instance SDA pad output; 0 pulls the line low, 1 releases it.
`smbsus_ni`	input	`logic [NUM_I2CS-1:0]`	Per-instance SMBus SUS in, active-low; synchronized and reported in SMBUS_STATUS.
`smbsus_no`	output	`logic [NUM_I2CS-1:0]`	Per-instance SMBus SUS out, active-low; high unless the instance is in host mode.
`smbalert_ni`	input	`logic [NUM_I2CS-1:0]`	Per-instance SMBus ALERT in, active-low; masked while I2C_CTRL.SMBUS_EN is low.
`smbalert_no`	output	`logic [NUM_I2CS-1:0]`	Per-instance SMBus ALERT out, active-low; high unless the instance is in target mode.
`controller_tx_ready_o`	output	`logic [NUM_I2CS-1:0]`	Per-instance controller TX DMA ready; low from FMT FIFO full until below threshold.
`controller_rx_ready_o`	output	`logic [NUM_I2CS-1:0]`	Per-instance controller RX DMA ready; high from above RX threshold until empty.
`target_tx_ready_o`	output	`logic [NUM_I2CS-1:0]`	Per-instance target TX DMA ready; low from TX FIFO full until below threshold.
`target_rx_ready_o`	output	`logic [NUM_I2CS-1:0]`	Per-instance target RX DMA ready; high from above ACQ threshold until empty.
`i2c_irq_o`	output	`logic [NUM_I2CS-1:0]`	Per-instance level interrupt; OR of the enabled INTR_STATE sources.
`i2c_debug_o`	output	`logic [NUM_I2CS-1:0][3:0]`	Per-instance four-bit debug; see i2c_core.