idma_backend_wrapper

Turn 1-D iDMA transfer requests into AXI master read and write traffic.

Each master interface has its own idma_backend_rw_axi with a hardware legalizer, zero-length rejection and no error handling; an axi_mux merges its read and write ports and an axi_cut registers the master port. NUM_MST_INTERFACES must be >= 1. BUFFER_DEPTH is the realignment buffer depth in beats and must be >= 2; 3 handles misaligned transfers efficiently. EN_R_AW_COUPLING is recommended.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NUM_MST_INTERFACES`	`int unsigned`	`1`	Backend master count; must be >= 1.
`DMA_MST_MAX_TXNS`	`int unsigned`	`16`	Max outstanding AXI transactions per master interface.
`M2B_FIFO_DEPTH`	`int unsigned`	`0`	Depth of the request FIFO ahead of each backend; 0 passes requests straight through.
`BUFFER_DEPTH`	`int unsigned`	`3`	Realignment buffer depth in beats; must be >= 2.
`EN_R_AW_COUPLING`	`bit`	`1`	Makes the backend's R-to-AW coupling hardware available; recommended.
`BYPASS_DMA_MST_FLOPS`	`bit`	`1'b0`	Bypasses the axi_cut registers on each master port.
`TF_LEN_WIDTH`	`int unsigned`	`32`	Transfer-length field width; the maximum transfer is 2**TF_LEN_WIDTH bytes.
`AXI_ADDR_WIDTH`	`int unsigned`	`56`	AXI address width.
`AXI_DATA_WIDTH`	`int unsigned`	`64`	Data width of the AXI master port and the backend transfer buffer.
`AXI_USER_WIDTH`	`int unsigned`	`12`	User-signal width of the AXI master port.
`MST_ID_WIDTH`	`int unsigned`	`3`	AXI master ID width; must equal BACKEND_INT_ID_WIDTH + 1.
`BACKEND_INT_ID_WIDTH`	`int unsigned`	`2`	ID width of idma_req_t and of the backend read and write ports; axi_mux widens it by one bit.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Async reset, active-low.
`test_en_i`	input	`logic`	DFT test enable for the request FIFO, the backend and the AXI mux.
`dma_backend_busy_o`	output	`logic`	High while any request is pending, any backend is busy, or any AW awaits its B or AR its last R.
`req_i`	input	`idma_req_t [NUM_MST_INTERFACES-1:0]`	Backend request payload.
`req_valid_i`	input	`logic [NUM_MST_INTERFACES-1:0]`	Backend request valid.
`req_ready_o`	output	`logic [NUM_MST_INTERFACES-1:0]`	Backend request ready.
`resp_o`	output	`idma_resp_t [NUM_MST_INTERFACES-1:0]`	Backend response payload.
`resp_valid_o`	output	`logic [NUM_MST_INTERFACES-1:0]`	Backend response valid.
`resp_ready_i`	input	`logic [NUM_MST_INTERFACES-1:0]`	Backend response ready.
`dma_mst_axi_req_o`	output	`dma_mst_req_t [NUM_MST_INTERFACES-1:0]`	AXI master request, registered by axi_cut unless BYPASS_DMA_MST_FLOPS.
`dma_mst_axi_resp_i`	input	`dma_mst_resp_t [NUM_MST_INTERFACES-1:0]`	AXI master response.