idma_frontend_wrapper
Accept AXI control traffic in an iDMA register frontend and emit 1-D iDMA requests.
Each control interface has its own chain: an axi_cut, an axi_dw_converter to 32-bit AXI, a second axi_cut, an axi_to_reg_v2 bridge to a 32-bit register interface, the idma_reg64_2d register frontend, a stream_fifo that buffers 2-D requests between the register frontend and the 2-D midend, and an idma_nd_midend that splits each 2-D request into 1-D requests. An idma_transfer_id_gen per interface issues transfer IDs and retires one on each midend completion. NUM_CTRL_INTERFACES and NUM_CTRL_STREAMS must be >= 1. F2M_FIFO_DEPTH is passed unchanged to the stream_fifo DEPTH and is the FIFO depth in requests; fifo_v3 asserts DEPTH > 0.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
NUM_CTRL_INTERFACES | int unsigned | 1 | Independent control ports, each with its own frontend, FIFO and midend; must be >= 1. |
NUM_CTRL_STREAMS | int unsigned | 1 | Register-frontend streams per control port; must be >= 1. The stream index is unconnected, so all streams share one FIFO and midend. |
F2M_FIFO_DEPTH | int unsigned | 4 | Depth in requests of the FIFO between the register frontend and the 2-D midend; passed unchanged to stream_fifo DEPTH and must be > 0. |
BYPASS_DMA_CTRL_FLOPS | bit | 1'b0 | When set, the control-port axi_cut is a pass-through with no registers. The axi_cut between the width converter and axi_to_reg_v2 is always registered. |
NUM_DIM | int unsigned | 2 | Transfer dimension count of the midend; the 2-D register frontend and two-entry RepWidths match only 2. |
REP_WIDTH | int unsigned | 32 | Width of each midend repetition counter. |
CTRL_ADDR_WIDTH | int unsigned | 9 | Ctrl AXI address width. |
CTRL_DATA_WIDTH | int unsigned | 64 | Ctrl AXI data width; must be >= 32. axi_dw_converter narrows it to the 32-bit register width. |
CTRL_ID_WIDTH | int unsigned | 8 | Ctrl AXI ID width. |
CTRL_USER_WIDTH | int unsigned | 12 | Ctrl AXI user width. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | logic | Frontend clock; the gated frontend clock in idma_wrapper. |
rst_ni | input | logic | Async reset, active-low. |
test_en_i | input | logic | Test mode, driven to the request FIFO testmode input. |
dma_frontend_wakeup_o | output | logic | High while any interface has an AXI control command in flight, a queued request, or a busy midend. |
dma_frontend_busy_o | output | logic | High while any request FIFO is non-empty or any midend is busy; in-flight AXI control commands are excluded. |
dma_ctrl_axi_req_i | input | dma_ctrl_req_t [NUM_CTRL_INTERFACES-1:0] | AXI control subordinate request per interface. |
dma_ctrl_axi_resp_o | output | dma_ctrl_resp_t [NUM_CTRL_INTERFACES-1:0] | AXI control subordinate response per interface. |
req_o | output | idma_req_t [NUM_CTRL_INTERFACES-1:0] | 1-D request from each midend. |
req_valid_o | output | logic [NUM_CTRL_INTERFACES-1:0] | Outbound request valid. |
req_ready_i | input | logic [NUM_CTRL_INTERFACES-1:0] | Outbound request ready. |
resp_i | input | idma_resp_t [NUM_CTRL_INTERFACES-1:0] | 1-D response to each midend. |
resp_valid_i | input | logic [NUM_CTRL_INTERFACES-1:0] | Response valid; a response with last set completes the 2-D transfer and retires its ID. |
resp_ready_o | output | logic [NUM_CTRL_INTERFACES-1:0] | Midend ready for the backend response. |