idma_request_manager_wrapper

Route frontend DMA requests onto one or more backend master ports.

NUM_CTRL_INTERFACES and NUM_MST_INTERFACES must be >= 1. With one of each the module is a combinational pass-through. Otherwise each master port round-robin arbitrates ctrl_req_* onto mst_req_*, a request already granted to a lower-numbered master is hidden from the others, and a 4-entry fifo_v3 per master records the originating control interface of each accepted request. Each mst_resp_* passes through a 1-entry buffer and returns, in request order, to the recorded control interface, where a round-robin arbiter picks between masters. A master receives no request while its tracking FIFO is full.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NUM_CTRL_INTERFACES`	`int unsigned`	`1`	Frontend request port count; must be >= 1.
`NUM_MST_INTERFACES`	`int unsigned`	`1`	Backend master count; must be >= 1.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Module clock; the gated backend clock in idma_wrapper.
`rst_ni`	input	`logic`	Async reset, active-low.
`test_en_i`	input	`logic`	Test mode, driven to the FIFO testmode inputs; unused in the pass-through configuration.
`ctrl_req_i`	input	`req_t [NUM_CTRL_INTERFACES-1:0]`	Frontend request payload.
`ctrl_req_valid_i`	input	`logic [NUM_CTRL_INTERFACES-1:0]`	Frontend request valid.
`ctrl_req_ready_o`	output	`logic [NUM_CTRL_INTERFACES-1:0]`	Frontend request ready; when arbitrating, high only for the request a master accepts.
`ctrl_resp_o`	output	`resp_t [NUM_CTRL_INTERFACES-1:0]`	Frontend response payload.
`ctrl_resp_valid_o`	output	`logic [NUM_CTRL_INTERFACES-1:0]`	Frontend response valid.
`ctrl_resp_ready_i`	input	`logic [NUM_CTRL_INTERFACES-1:0]`	Frontend response ready.
`mst_req_o`	output	`req_t [NUM_MST_INTERFACES-1:0]`	Backend request payload.
`mst_req_valid_o`	output	`logic [NUM_MST_INTERFACES-1:0]`	Backend request valid; held low while that master's tracking FIFO is full.
`mst_req_ready_i`	input	`logic [NUM_MST_INTERFACES-1:0]`	Backend request ready.
`mst_resp_i`	input	`resp_t [NUM_MST_INTERFACES-1:0]`	Backend response payload.
`mst_resp_valid_i`	input	`logic [NUM_MST_INTERFACES-1:0]`	Backend response valid.
`mst_resp_ready_o`	output	`logic [NUM_MST_INTERFACES-1:0]`	Backend response ready; when arbitrating, high while that master's response buffer is empty.