idma_wrapper
Assemble the iDMA frontend, request manager, backend, and optional clock gating.
Each control port feeds a register frontend and a 2D midend. The request manager distributes the resulting linear requests round-robin across the backends, one per master port. The frontend clock is gated by an AXI snoop of control port 0 only, so traffic on another control port does not wake it. The request manager and the backends share a second gated clock that runs while the frontend or a backend is busy.
Parameter constraints:
- NUM_CTRL_INTERFACES and NUM_MST_INTERFACES must be >= 1.
- NUM_CTRL_STREAMS must be between 1 and 16.
- CTRL_OUTSTANDING_TX covers all in-flight transactions the ctrl port admits for the frontend clock-gate snoop and must cover what the upstream fabric can present on dma_ctrl_axi_req_i[0].
- F2M_FIFO_DEPTH has a minimum depth of 1; otherwise the dma ctrl read bus stalls on command start.
- BUFFER_DEPTH is the realignment buffer depth in beats and must be >= 2.
- MST_ID_WIDTH must equal BACKEND_INT_ID_WIDTH + 1.
- AXI_DATA_WIDTH must be >= 32, the width of the DMA register interface.
- EN_R_AW_COUPLING is recommended.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
NUM_CTRL_INTERFACES | int unsigned | 1 | Number of AXI4 control ports, each with its own register frontend and 2D midend; must be >= 1. |
NUM_CTRL_STREAMS | int unsigned | 1 | Streams per control port, from 1 to 16. The register file always has 16 stream banks; reading NEXT_ID of a bank at or above this count starts no transfer. |
NUM_MST_INTERFACES | int unsigned | 1 | Number of AXI4 master ports, each with its own iDMA backend; must be >= 1. |
DMA_MST_MAX_TXNS | int unsigned | 16 | Maximum AXI transactions each backend keeps in flight on its master port. |
CTRL_OUTSTANDING_TX | int unsigned | 16 | Outstanding-transaction capacity of the frontend clock-gate snoop on control port 0. Must cover what the upstream fabric can present on dma_ctrl_axi_req_i[0]. |
F2M_FIFO_DEPTH | int unsigned | 4 | Depth of the command FIFO between each register frontend and its 2D midend. Minimum depth of 1; otherwise the dma ctrl read bus stalls on command start. |
M2B_FIFO_DEPTH | int unsigned | 0 | Depth of the request FIFO between the request manager and each backend; 0 connects them directly. |
BUFFER_DEPTH | int unsigned | 3 | Depth in beats of each backend's realignment buffer; must be >= 2. |
EN_R_AW_COUPLING | bit | 1 | Instantiates the backend R-AW coupling logic, which can hold a write address until its read data arrives; recommended. |
BYPASS_DMA_CTRL_FLOPS | bit | 1'b0 | Removes the register slice on each control port. |
BYPASS_DMA_MST_FLOPS | bit | 1'b0 | Removes the register slice on each master port. |
CG_HYSTERESIS_W | int unsigned | 6 | Width of cg_hysteresis_i, which bounds the idle wait of both clock gates to 2**CG_HYSTERESIS_W - 1 cycles. |
AXI_ADDR_WIDTH | int unsigned | 56 | Address width of the master ports, and the width of the transfer addresses, lengths and strides. |
AXI_DATA_WIDTH | int unsigned | 64 | Data width of both the control AXI port and the AXI master port; must be >= 32. |
AXI_USER_WIDTH | int unsigned | 12 | User-signal width of both the control AXI port and the AXI master port. |
CTRL_ID_WIDTH | int unsigned | 8 | ID width of the control ports; must match the ID field of dma_ctrl_req_t. |
MST_ID_WIDTH | int unsigned | 3 | ID width of the master ports; must match the ID field of dma_mst_req_t and equal BACKEND_INT_ID_WIDTH + 1. |
BACKEND_INT_ID_WIDTH | int unsigned | 2 | ID width of the iDMA request and of the separate read and write managers inside each backend; the backend mux adds one bit to form the master-port ID. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | logic | Clock; the frontend, request manager and backends run on gated copies of it. |
rst_ni | input | logic | Active-low reset. The iDMA submodules reset asynchronously and the clock gates and interrupt flop synchronously, so deassert it synchronously to clk_i. |
test_en_i | input | logic | Scan test enable, active-high; forces both clock gates open and is forwarded to every submodule. |
dma_busy_o | output | logic | High while a command is queued or in a 2D midend, or a backend has a request pending, a transfer active or an AXI response outstanding. |
dma_intp_o | output | logic | Completion interrupt: a registered one-cycle pulse in the cycle after dma_busy_o falls, with no enable or mask. |
cg_enable_i | input | logic | Enables both clock gates when high; while it is low both gated clocks run continuously. |
cg_hysteresis_i | input | logic [CG_HYSTERESIS_W-1:0] | Idle clk_i cycles each clock gate waits after activity ends before it stops its clock. |
dma_ctrl_axi_req_i | input | dma_ctrl_req_t [NUM_CTRL_INTERFACES-1:0] | AXI4 control-port requests; each port is converted to 32-bit DMA register accesses. |
dma_ctrl_axi_resp_o | output | dma_ctrl_resp_t [NUM_CTRL_INTERFACES-1:0] | AXI4 control-port responses. |
dma_mst_axi_req_o | output | dma_mst_req_t [NUM_MST_INTERFACES-1:0] | AXI4 master-port requests carrying the transfer reads and writes. |
dma_mst_axi_resp_i | input | dma_mst_resp_t [NUM_MST_INTERFACES-1:0] | AXI4 master-port responses. |
frontend_clk_active_o | output | logic | High while the frontend gated clock is running. |
frontend_bus_active_o | output | logic | High while control port 0 has an AXI transaction outstanding. |