jtag2axi
Generate single-beat AXI4 transactions from JTAG scan-chain inputs.
All scan chains share one shift register, captured and shifted on rising TCK, and one update latch loaded on falling TCK; series reads and writes pipeline. AXISeriesCtrl.pipeline_depth programs 0..FIFO_DEPTH, larger values saturate, and the effective depth is pipeline_depth + 1. Every transaction carries ID 0, user 0, one INCR beat, AxCACHE 0b0010 and AxPROT 0b000. A scanned size wider than the bus is taken as one full beat: AxSIZE, the series write strobes, the series address step and the series data length all use the bus width.
The following logic lives in the TCK domain:
- TAP scan
- command dispatch
- AXI master FSM
- series request/response FIFOs
- sticky status
The AXI master crosses into ACLK through one axi_cdc_clearable instance. A reset on either trst_ni or arst_ni runs its isolate-and-clear sequence on both sides. An ACLK-domain output stage buffers AW, W and AR, issues AW and W only as a pair, bounds outstanding transactions, and drains responses to requests issued before a CDC clear. When the clear reaches the TCK side, the bridge aborts every operation in flight or queued: the FSM returns to idle and holds there until the clear completes, the series FIFOs and pipeline accounting are flushed, and the status that reports an aborted operation reads DECERR. The sticky series status takes DECERR only while it holds no earlier error. Every other status, and the SERIES_CTRL configuration, is kept.
Parameter constraints:
- Address and data widths are parametrizable; DATA_WIDTH must be a power of 2 and a multiple of 8.
- ATOP_WIDTH must be 6 to match the PULP AXI channel typedef layout.
- ADDR_WIDTH must cover the byte offset within one data beat.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
ADDR_WIDTH | int | 52 | Address width. |
DATA_WIDTH | int | 64 | Width of AXI read and write data and of the scan-chain data fields; a power of 2 from 8 to 1024. |
ID_WIDTH | int | 1 | AXI ID width; IDs are always driven zero. |
USER_WIDTH | int | 1 | AXI user width; user fields are always driven zero. |
FIFO_DEPTH | int | 2 | Largest programmable AXISeriesCtrl.pipeline_depth; the series request FIFO holds FIFO_DEPTH + 1 entries. |
ATOP_WIDTH | int | 6 | AWATOP width; must be 6 for PULP AXI typedefs. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
tck_i | input | logic | JTAG Test Clock. |
trst_ni | input | logic | JTAG Test Reset (active low); resets all TCK-domain state and the CDC source side. |
scan_in_i | input | logic | JTAG Scan Data In (TDI). |
scan_out_o | output | logic | JTAG Scan Data Out (TDO), bit 0 of the shared shift register. |
capture_en_i | input | logic | JTAG Capture Enable (Capture-DR state). |
shift_en_i | input | logic | JTAG Shift Enable (Shift-DR state). |
update_en_i | input | logic | JTAG Update Enable (Update-DR state). |
select_AXISingleOp_i | input | logic | Select AXISingleOp scan chain. |
select_AXISeriesCtrl_i | input | logic | Select AXISeriesCtrl scan chain. |
select_AXISeriesDataIncr_i | input | logic | Select AXISeriesDataIncr scan chain. |
select_AXISeriesDataNoIncr_i | input | logic | Select AXISeriesDataNoIncr scan chain. |
select_AXISeriesDataWithErrorStatus_i | input | logic | Select AXISeriesDataWithErrorStatus scan chain. |
security_disable_i | input | logic | Active-high bridge disable: blocks Update-DR, keeps the AXI FSM idle, and flushes queued requests once the FSM is idle. |
aclk_i | input | logic | AXI Clock. |
arst_ni | input | logic | AXI Reset (active low), for the CDC destination side and the ACLK output stage. |
test_en_i | input | logic | DFT test-mode enable, active-high, for the ACLK output stage fall-through registers. |
awid_o | output | logic [ID_WIDTH-1:0] | Write-address ID, always zero. |
awaddr_o | output | logic [ADDR_WIDTH-1:0] | Write address. |
awlen_o | output | logic [7:0] | Write burst length, always zero for a single beat. |
awsize_o | output | logic [2:0] | Write beat size: the scanned size, at most the bus width. |
awburst_o | output | logic [1:0] | Write burst type, always INCR. |
awlock_o | output | logic | Write lock, always zero. |
awcache_o | output | logic [3:0] | Write cache attributes, always 0b0010. |
awprot_o | output | logic [2:0] | Write protection attributes, always 0b000. |
awqos_o | output | logic [3:0] | Write QoS, always zero. |
awregion_o | output | logic [3:0] | Write region, always zero. |
awuser_o | output | logic [USER_WIDTH-1:0] | Write-address user, always zero. |
awatop_o | output | logic [ATOP_WIDTH-1:0] | Write atomic op (AWATOP), always zero. |
awvalid_o | output | logic | Write-address valid. |
awready_i | input | logic | Write-address ready. |
wdata_o | output | logic [DATA_WIDTH-1:0] | Write data. |
wstrb_o | output | logic [DATA_WIDTH/8-1:0] | Write strobes. |
wlast_o | output | logic | Write last, always high for the single beat. |
wuser_o | output | logic [USER_WIDTH-1:0] | Write-data user, always zero. |
wvalid_o | output | logic | Write-data valid. |
wready_i | input | logic | Write-data ready. |
bid_i | input | logic [ID_WIDTH-1:0] | Write-response ID. |
bresp_i | input | logic [1:0] | Write-response status. |
buser_i | input | logic [USER_WIDTH-1:0] | Write-response user. |
bvalid_i | input | logic | Write-response valid. |
bready_o | output | logic | Write-response ready. |
arid_o | output | logic [ID_WIDTH-1:0] | Read-address ID, always zero. |
araddr_o | output | logic [ADDR_WIDTH-1:0] | Read address. |
arlen_o | output | logic [7:0] | Read burst length, always zero for a single beat. |
arsize_o | output | logic [2:0] | Read beat size: the scanned size, at most the bus width. |
arburst_o | output | logic [1:0] | Read burst type, always INCR. |
arlock_o | output | logic | Read lock, always zero. |
arcache_o | output | logic [3:0] | Read cache attributes, always 0b0010. |
arprot_o | output | logic [2:0] | Read protection attributes, always 0b000. |
arqos_o | output | logic [3:0] | Read QoS, always zero. |
arregion_o | output | logic [3:0] | Read region, always zero. |
aruser_o | output | logic [USER_WIDTH-1:0] | Read-address user, always zero. |
arvalid_o | output | logic | Read-address valid. |
arready_i | input | logic | Read-address ready. |
rid_i | input | logic [ID_WIDTH-1:0] | Read-data ID. |
rdata_i | input | logic [DATA_WIDTH-1:0] | Read data. |
rresp_i | input | logic [1:0] | Read-response status. |
rlast_i | input | logic | Read last. |
ruser_i | input | logic [USER_WIDTH-1:0] | Read-data user. |
rvalid_i | input | logic | Read-data valid. |
rready_o | output | logic | Read-data ready. |