key_manager

Integrate the Key Manager CPU, memories, peripherals and crypto master ports into one hierarchical block.

Components:

PicoRV32 CPU with direct ROM/SRAM memory interfaces
AXI-Lite crossbar for internal peripheral access
KMCSR (control/status registers) with IRQ aggregation
Mailbox for bidirectional SEP-KM communication
DRBG sampler for random number acquisition
KPV (Key and Policy Vault) for key storage
External crypto engine master ports (OTBN, AES, KMAC, HMAC, Adams Bridge) and the OTP/eFuse master

km_reset_conditioner conditions reset internally and produces two clean resets:

Cold (AASD, rst_cold_aasd_no): resets all KM components; source is cold_rst_ni.
Warm (synchronous, rst_warm_sync_no): resets the CPU, the internal AXI fabric and the warm KMCSR/KPV/DRBG/mailbox fields; sources are warm_rst_ni, soft_rst_n from KMCSR and cold reset.

LATCHED_MEM_RDATA is 1 when ROM/SRAM latch read data, so it stays valid after the request deasserts, and 0 when read data is valid only while rvalid is asserted. Setting it lets the CPU use look-ahead optimization when the memory supports it.

OTP_EFUSE_REMAP_BASE is the absolute address of the eFuse controller as seen on efuse_req_o. Transactions from the internal OTP crossbar port (xbar port 8, the KM-local OTP page) that fall in the MAP, CTRL or MMR register map keep their page offset, the low km_intf_pkg::OtpRemapAddrWidth bits, and take their upper bits from OTP_EFUSE_REMAP_BASE before being driven onto efuse_req_o. Every other offset in the page completes locally with SLVERR and never reaches efuse_req_o. The integrator sets OTP_EFUSE_REMAP_BASE to the page-aligned system-level address of the eFuse controller and must connect efuse_req_o/efuse_resp_i to that controller.

The ROM and SRAM hard macros are instantiated at integration level and connect through the exposed memory ports.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`ROM_SIZE_BYTES`	`int unsigned`	`16384`	Size of the KM boot ROM in bytes. Must equal the ROM window of the KM memory map in km_intf_pkg.
`SRAM_SIZE_BYTES`	`int unsigned`	`32768`	Size of the KM data SRAM in bytes. Must equal the SRAM window of the KM memory map in km_intf_pkg.
`MAILBOX_DEPTH`	`int unsigned`	`16`	Words per mailbox FIFO direction. Must be a power of two from 16 to 256.
`LATCHED_MEM_RDATA`	`bit`	`1'b0`	1 if ROM/SRAM keep read data valid after the request deasserts, which lets the CPU use it directly for look-ahead.
`OTP_EFUSE_REMAP_BASE`	`km_addr_t`	`32'h1093_0000`	Absolute eFuse controller address on efuse_req_o; replaces the bits above the OTP page offset. Page-aligned.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`cold_rst_ni`	input	`logic`	Cold reset, asynchronous active-low; the conditioner releases it synchronously to clk_i.
`warm_rst_ni`	input	`logic`	Warm reset, active-low and synchronous to clk_i; the warm reset stays asserted at least 10 clk_i cycles after it releases.
`mbox_sep_req_i`	input	`km_axil_req_t`	Mailbox AXI4-Lite slave request from the SEP host, which sends and receives messages to and from KM here.
`mbox_sep_resp_o`	output	`km_axil_resp_t`	Mailbox AXI4-Lite slave response to the SEP host.
`mbox_irq_to_sep_o`	output	`logic`	Level mailbox interrupt to the SEP: OR of the SEP-side sources (outbound data available, inbound space available, inbound overflow, outbound underflow, flushed by KM) masked by SEP_IRQ_ENABLE.
`unrecoverable_err_o`	output	`logic`	Active-high: KM is in trap state (no longer executing).
`recoverable_err_o`	output	`logic`	Level of the firmware-written KMCSR RECOVERABLE_ERR register bit.
`otbn_req_o`	output	`km_axil_req_t`	External crypto AXI4-Lite master to OTBN (Big Number Accelerator).
`otbn_resp_i`	input	`km_axil_resp_t`	AXI4-Lite response from OTBN.
`aes_req_o`	output	`km_axil_req_t`	External crypto AXI4-Lite master to the AES accelerator.
`aes_resp_i`	input	`km_axil_resp_t`	AXI4-Lite response from the AES accelerator.
`kmac_req_o`	output	`km_axil_req_t`	External crypto AXI4-Lite master to the KMAC accelerator.
`kmac_resp_i`	input	`km_axil_resp_t`	AXI4-Lite response from the KMAC accelerator.
`hmac_req_o`	output	`km_axil_req_t`	External crypto AXI4-Lite master to the HMAC accelerator.
`hmac_resp_i`	input	`km_axil_resp_t`	AXI4-Lite response from the HMAC accelerator.
`abr_req_o`	output	`km_axil_req_t`	External crypto AXI4-Lite master to the Adams Bridge accelerator.
`abr_resp_i`	input	`km_axil_resp_t`	AXI4-Lite response from the Adams Bridge accelerator.
`abr_mlkem_sharedkey_irq_i`	input	`logic`	Adams Bridge ML-KEM shared-key valid IRQ (level-sensitive, active-high).
`efuse_req_o`	output	`km_axil_req_t`	OTP/eFuse AXI-Lite master from xbar port 8, carrying only MAP/CTRL/MMR accesses, remapped to OTP_EFUSE_REMAP_BASE.
`efuse_resp_i`	input	`km_axil_resp_t`	AXI-Lite response from the system eFuse controller.
`rom_mem_req_o`	output	`km_rom_mem_req_t`	Request to the ROM hard macro.
`rom_mem_rsp_i`	input	`km_rom_mem_rsp_t`	Response from the ROM hard macro.
`sram_mem_req_o`	output	`km_sram_mem_req_t`	Request to the SRAM hard macro.
`sram_mem_rsp_i`	input	`km_sram_mem_rsp_t`	Response from the SRAM hard macro.
`drbg_axis_req_i`	input	`km_drbg_axis_req_t`	DRBG AXI-Stream request (KM is slave, DRBG is master).
`drbg_axis_resp_o`	output	`km_drbg_axis_resp_t`	DRBG AXI-Stream response.
`otp_data_i`	input	`km_otp_data_t`	Differentially encoded SEP OTP data.
`wipe_state_i`	input	`logic`	Wipe state. A rising edge sets IRQ_STATUS.WIPE_STATE and zeros the entire KPV on the next cycle. It is ORed with the CPU trap before edge detection, so a CPU trap wipes the same way and masks this input while it lasts.
`test_en_i`	input	`logic`	DFT test-enable, active-high; selects scan_rst_ni for both conditioned resets and drives the crossbar and mailbox test inputs.
`scan_rst_ni`	input	`logic`	Scan reset, active-low; replaces both the cold and warm conditioned resets while test_en_i is high.