km_drbg_sampler

Bridge Key Manager CPU AXI4-Lite reads of the sampler registers to a DRBG AXI-Stream.

Mapped at base 0x0001_5000. A CPU read of the DATA register either returns a prefetched random word or initiates a new DRBG request via the AXI-Stream handshake, packing the TSTRB-valid bytes of successive beats from lane 0 upward until four are collected. A configurable timeout (CFG.TIMEOUT, 0 disables) protects against DRBG stalls during active reads; a timeout or stream protocol violation answers the DATA read with SLVERR and zero data. While CFG.PREFETCH is set, one word is kept prefetched and refilled after each use. drbg_error_o pulses on a timeout or a stream protocol violation.

DATA
CFG (PREFETCH, TIMEOUT)
STATUS (DRBG_READY, PREFETCHED, TIMEOUT_ERR, STREAM_ERR, COUNT_GOOD, COUNT_BAD)
PREFETCH_DATA (read-only)

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`cold_rst_ni`	input	`logic`	Cold reset: AASD.
`warm_rst_ni`	input	`logic`	Warm reset: fully synchronous.
`axil_req_i`	input	`axil_req_t`	AXI4-Lite slave request from the crossbar (base 0x0001_5000); only address bits [3:0] are decoded, and one read is outstanding at a time.
`axil_resp_o`	output	`axil_resp_t`	AXI4-Lite slave response to the crossbar.
`drbg_axis_req_i`	input	`km_drbg_axis_req_t`	DRBG AXI-Stream TVALID, TDATA, TSTRB in (KM is slave); TUSER is ignored.
`drbg_axis_resp_o`	output	`km_drbg_axis_resp_t`	DRBG AXI-Stream TREADY out; high while a DATA read or a prefetch is collecting bytes.
`drbg_error_o`	output	`logic`	Aggregated error pulse to KMCSR (sets IRQ_STATUS.DRBG_ERR).