km_mailbox

Exchange messages between SEP and KM through two FIFOs behind independent AXI4-Lite slave interfaces.

Two synchronous FIFOs sit between the KM-side and SEP-side slaves:

Inbound FIFO (SEP -> KM): SEP writes via WRITE_DATA, KM reads via READ_DATA.
Outbound FIFO (KM -> SEP): KM writes via WRITE_DATA, SEP reads via READ_DATA.

Each FIFO word carries a 1-bit separator tag for message framing, taken from the writer's WRITE_SEPARATOR register, which hardware clears after the next push, and shown in both sides' STATUS when the reader pops the word. WRITE_DATA / READ_DATA addresses are handled as direct FIFO push/pop; STATUS and IRQ registers are served by RDL-generated register blocks.

Overflow and underflow responses are configurable per side (SLVERR or OKAY). Both sides can flush all FIFOs via CTRL.FLUSH. Each side ORs its IRQ from data-available and write-space-available (level) plus sticky overflow / underflow / flushed-by-peer events, each masked by that side's IRQ_ENABLE.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`MAILBOX_DEPTH`	`int unsigned`	`16`	Words per FIFO direction.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`cold_rst_ni`	input	`logic`	Cold reset: AASD; resets the FIFOs and SEP-facing interfaces.
`warm_rst_ni`	input	`logic`	Warm reset: synchronous; resets the KM-CPU-facing interfaces.
`test_en_i`	input	`logic`	DFT test-enable; unused.
`km_axil_req_i`	input	`km_axil_req_t`	KM CPU AXI4-Lite slave request: pushes the outbound FIFO, pops the inbound FIFO and reaches the KM-side registers.
`km_axil_resp_o`	output	`km_axil_resp_t`	KM CPU AXI4-Lite slave response.
`sep_axil_req_i`	input	`sep_axil_req_t`	SEP host AXI4-Lite slave request: pushes the inbound FIFO, pops the outbound FIFO and reaches the SEP-side registers.
`sep_axil_resp_o`	output	`sep_axil_resp_t`	SEP host AXI4-Lite slave response.
`mbox_irq_to_km_o`	output	`logic`	Level IRQ to the KM CPU: OR of the KM-side sources masked by KM_IRQ_ENABLE.
`mbox_irq_to_sep_o`	output	`logic`	Level IRQ to the SEP host: OR of the SEP-side sources masked by SEP_IRQ_ENABLE.