km_reset_conditioner

Condition the Key Manager resets into a cold (AASD) and a warm (synchronous) output.

Both outputs are clean, glitch-free and active-low.

Cold path (rst_cold_aasd_no):

Warm path (rst_warm_sync_no):

Synchronous sources: warm_rst_ni (external pulse) or soft_rst_ni (KMCSR software trigger); both are assumed synchronous to clk_i.
Cold source: rst_cold_aasd_no is the async reset of the warm counter flop, so any cold-reset event immediately asserts rst_warm_sync_no and clears all warm-reset-only state.
Pulse extension: held for at least MIN_RESET_CYCLES after the last trigger cycle.
In key_manager it resets the PicoRV32 CPU, the internal AXI fabric, and the warm fields of KMCSR, KPV, the DRBG sampler and the mailbox.

DFT: scan_rst_ni / scanmode_i bypass both output paths consistently.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`MIN_RESET_CYCLES`	`int unsigned`	`10`	Minimum warm reset hold in clk_i cycles after the trigger releases; must be at least 2.

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`cold_rst_ni`	input	`logic`	Async cold reset (active-low, from external system).
`soft_rst_ni`	input	`logic`	Soft reset (active-low, from KMCSR; sync to clk_i).
`warm_rst_ni`	input	`logic`	Warm reset pulse (active-low, from integrator; sync to clk_i).
`scan_rst_ni`	input	`logic`	Scan reset (active-low, for DFT).
`scanmode_i`	input	`mubi4_t`	Scan mode (MuBi4True enables scan override on both outputs).
`rst_cold_aasd_no`	output	`logic`	Cold reset: async-assert / sync-deassert (AASD).
`rst_warm_sync_no`	output	`logic`	Warm reset: registered on clk_i, and asserted asynchronously while rst_cold_aasd_no is low.