km_rom_interface

Adapt the PicoRV32 native memory interface to the ROM with parity checking and look-ahead prefetch.

Bridges the PicoRV32 native memory interface to the standard ROM memory interface (km_rom_mem_req_t / km_rom_mem_rsp_t). Read-only: write attempts are immediately acknowledged and reported as errors on rom_write_err_o.

Supports the PicoRV32 look-ahead interface for efficient prefetching: mem_la_read_i / mem_la_addr_i arrive one cycle before mem_valid_i, allowing the ROM to begin the fetch early.

Odd parity is checked per byte on the read-strobe lanes of every read response; a mismatch raises parity_error_o for the cycle the response is valid. Requests are held off for two cycles after reset release.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`ROM_ADDR_WIDTH`	`int unsigned`	`KM_ROM_MEM_ADDR_WIDTH`	Word-address width for the ROM.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low asynchronous reset.
`mem_valid_i`	input	`logic`	PicoRV32 native memory request valid (from CPU).
`mem_ready_o`	output	`logic`	Memory ready: read data valid, or immediately for a write.
`mem_addr_i`	input	`logic [31:0]`	Byte address.
`mem_wdata_i`	input	`logic [31:0]`	Write data (unused, ROM is read-only).
`mem_wstrb_i`	input	`logic [3:0]`	Write strobe; any set bit marks a write, which is acknowledged without effect and flagged on rom_write_err_o.
`mem_rstrb_i`	input	`logic [3:0]`	Read strobe: byte lanes consumed by the CPU, which select the parity-checked lanes.
`mem_rdata_o`	output	`logic [31:0]`	Read data.
`mem_la_read_i`	input	`logic`	Look-ahead read signal (1 cycle before mem_valid).
`mem_la_addr_i`	input	`logic [31:0]`	Look-ahead address.
`mem_la_rstrb_i`	input	`logic [3:0]`	Look-ahead read strobe; selects the parity-checked lanes of a look-ahead fetch.
`rom_mem_req_o`	output	`km_rom_mem_req_t`	ROM memory request, exposed at the subsystem boundary.
`rom_mem_rsp_i`	input	`km_rom_mem_rsp_t`	ROM memory response.
`parity_error_o`	output	`logic`	Combinational; high while a valid read response fails parity on a strobed lane.
`rom_write_err_o`	output	`logic`	Combinational; high while mem_valid_i is high with a nonzero write strobe.