picorv32_pcpi_crc

Decode the Key Manager CRC custom instructions as the PicoRV32 PCPI front-end.

Recognizes custom-0 opcodes with the CRC funct7/funct3 encodings, latches rs1/rs2 as CRC state and data, and drives km_crc_engine until completion. pcpi_wait_o stalls the CPU while busy; pcpi_ready_o and pcpi_wr_o present the engine result on pcpi_rd_o for one cycle.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low asynchronous reset.
`pcpi_valid_i`	input	`logic`	PicoRV32 presents a candidate instruction.
`pcpi_insn_i`	input	`logic [31:0]`	Instruction word under decode.
`pcpi_rs1_i`	input	`logic [31:0]`	rs1 value used as CRC state / seed.
`pcpi_rs2_i`	input	`logic [31:0]`	rs2 value used as CRC data; byte modes use bits [7:0].
`pcpi_wr_o`	output	`logic`	Write-back enable for pcpi_rd_o.
`pcpi_rd_o`	output	`logic [31:0]`	CRC result returned to the CPU.
`pcpi_wait_o`	output	`logic`	Stall request while the CRC engine runs.
`pcpi_ready_o`	output	`logic`	One-cycle ready pulse with a valid result.