picorv32_wrapper
Run the PicoRV32 core and route its native memory interface to ROM, SRAM and an AXI4-Lite peripheral master.
Instantiates the PicoRV32 core (RV32EMC: 16 registers, M extension, compressed ISA) and routes the native memory interface by address to three targets:
- ROM (read-only, via km_rom_interface with parity checking).
- SRAM (read/write, via km_sram_interface with scrambling, parity, and write-lock enforcement).
- Peripherals: every other address, via picorv32_axi_adapter to an AXI4-Lite master.
With OCAH_KM_VROM defined, the virtual ROM window (VromBaseAddr to VromEndAddr) is decoded to the vrom_mem_* nets instead, which complete an access only when the simulation drives vrom_mem_ready. The define is simulation-only: elaboration fails when SYNTHESIS or EMULATION is also defined. Without it the window is a peripheral address.
Three external IRQ sources connect to the PicoRV32 as non-latched level-sensitive inputs:
- Bit 3: KMCSR aggregated interrupt (sticky error sources).
- Bit 4: Mailbox interrupt (level); in key_manager the mailbox's aggregated KM-side IRQ.
- Bit 5: Adams Bridge ML-KEM shared-key valid.
AXI bus errors (SLVERR, DECERR) on the write and read response channels are detected and reported as pulse outputs to KMCSR.
An execute-permission whitelist is enforced on committed instruction fetches (mem_instr). Allowed regions are selected by sram_exec_mode_i (from KMCSR SRAM_EXEC_MODE.enable) and by the ROM lockout:
- 0 (ROM mode): ROM only.
- 1 (SRAM mode): write-locked SRAM regions, plus the ROM until the lockout engages on the first fetch from a write-locked SRAM region. The lockout holds until rst_sync_ni; afterwards ROM fetches and data reads complete at once with zero data.
Under OCAH_KM_VROM, the virtual ROM window is executable in both modes and exempt from the lockout.
Any fetch outside the whitelist pulses exec_violation_o, except a blocked ROM access, which pulses rom_access_violation_o instead.
LATCHED_MEM_RDATA is 1 when ROM/SRAM latch read data, so it stays valid after the request deasserts, and 0 when read data is valid only while rvalid is asserted. Setting it makes the core use mem_rdata directly instead of its own capture register.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
ROM_ADDR_WIDTH | int unsigned | km_intf_pkg::KM_ROM_MEM_ADDR_WIDTH | ROM word-address width. |
SRAM_ADDR_WIDTH | int unsigned | km_intf_pkg::KM_SRAM_MEM_ADDR_WIDTH | SRAM word-address width. |
LATCHED_MEM_RDATA | bit | 1'b0 | 1 if ROM/SRAM latch read data. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | logic | System clock. |
rst_ni | input | logic | Active-low async reset for the memory interfaces, PCPI CRC, read-data select and AXI error logic. |
rst_sync_ni | input | logic | Active-low synchronous reset for the PicoRV32 core, the AXI adapter and the ROM lockout latch. |
rom_mem_req_o | output | km_rom_mem_req_t | ROM interface request (with parity checking). |
rom_mem_rsp_i | input | km_rom_mem_rsp_t | ROM interface response. |
rom_parity_err_o | output | logic | ROM parity error detected (pulse). |
rom_write_err_o | output | logic | ROM write attempt detected (pulse). |
sram_mem_req_o | output | km_sram_mem_req_t | SRAM interface request (with scrambling and parity checking). |
sram_mem_rsp_i | input | km_sram_mem_rsp_t | SRAM interface response. |
sram_parity_err_o | output | logic | SRAM parity error detected (pulse). |
scrambler_key_i | input | logic [31:0] | Scrambler key from KMCSR, passed through to the SRAM interface. |
scrambler_en_i | input | logic | Scrambler enable from KMCSR, passed through to the SRAM interface. |
sram_lock_bits_i | input | logic [31:0] | SRAM write-lock (KMCSR): bit[i]=1 locks region i. |
sram_write_lock_violation_region_o | output | logic [31:0] | SRAM write-lock violation to KMCSR: one-hot region that had an attempted write while locked. |
sram_exec_mode_i | input | logic | Execute-permission whitelist mode from KMCSR: 0=ROM-only, 1=write-locked-SRAM. |
exec_violation_o | output | logic | Execute-permission whitelist violation to KMCSR: pulse on a committed fetch outside the whitelist. |
rom_access_violation_o | output | logic | ROM lockout violation to KMCSR: pulse on a ROM fetch or data read after lockout engages. |
axi_mst_req_o | output | axil_req_t | AXI4-Lite master request to the peripherals via the crossbar. |
axi_mst_resp_i | input | axil_resp_t | AXI4-Lite master response from the crossbar. |
irq_i | input | logic | KMCSR aggregated interrupt (sticky error sources). |
mbox_irq_i | input | logic | Mailbox interrupt (level-sensitive). |
abr_sharedkey_irq_i | input | logic | ML-KEM shared-key valid (level-sensitive). |
irq_entry_addr_i | input | logic [31:0] | Runtime IRQ handler entry PC from KMCSR (reset default 0x0000_0010). |
trap_o | output | logic | PicoRV32 trap output; in key_manager it wipes the KPV and drives unrecoverable_err_o. |
axi_slverr_o | output | logic | AXI SLVERR error detected (pulse to KMCSR IRQ). |
axi_decerr_o | output | logic | AXI DECERR error detected (pulse to KMCSR IRQ). |