log_engine_pkg

Define AXI-Lite typedefs and constants for the log engine.

Types the CSR port (register-block minimum address width, 32-bit data), the log-fetch port (56-bit address, 64-bit data) and the log-write port (32-bit address and data). Also defines the 16-entry log ring, the 512 KiB maximum log region and its alignment, the derived length, index and counter types, and the fetch and write FSM states.

`reg_addr_t`

Alias for logic [RegAddrWidth-1:0]

`reg_data_t`

Alias for logic [RegDataWidth-1:0]

`reg_strb_t`

Alias for logic [RegStrbWidth-1:0]

`csr_axil_aw_chan_t`

Packed struct

Table 1. `csr_axil_aw_chan_t`
Field	Type	Description
`addr`	`reg_addr_t`
`prot`	`axi_pkg::prot_t`

`csr_axil_w_chan_t`

Packed struct

Table 2. `csr_axil_w_chan_t`
Field	Type	Description
`data`	`reg_data_t`
`strb`	`reg_strb_t`

`csr_axil_b_chan_t`

Packed struct

Table 3. `csr_axil_b_chan_t`
Field	Type	Description
`resp`	`axi_pkg::resp_t`

`csr_axil_ar_chan_t`

Packed struct

Table 4. `csr_axil_ar_chan_t`
Field	Type	Description
`addr`	`reg_addr_t`
`prot`	`axi_pkg::prot_t`

`csr_axil_r_chan_t`

Packed struct

Table 5. `csr_axil_r_chan_t`
Field	Type	Description
`data`	`reg_data_t`
`resp`	`axi_pkg::resp_t`

`csr_axil_req_t`

Packed struct

Table 6. `csr_axil_req_t`
Field	Type	Description
`aw`	`csr_axil_aw_chan_t`
`aw_valid`	`logic`
`w`	`csr_axil_w_chan_t`
`w_valid`	`logic`
`b_ready`	`logic`
`ar`	`csr_axil_ar_chan_t`
`ar_valid`	`logic`
`r_ready`	`logic`

`csr_axil_resp_t`

Packed struct

Table 7. `csr_axil_resp_t`
Field	Type	Description
`aw_ready`	`logic`
`w_ready`	`logic`
`b`	`csr_axil_b_chan_t`
`b_valid`	`logic`
`ar_ready`	`logic`
`r`	`csr_axil_r_chan_t`
`r_valid`	`logic`

`log_fetch_addr_t`

Alias for logic [LogFetchAddrWidth-1:0]

`log_fetch_data_t`

Alias for logic [LogFetchDataWidth-1:0]

`log_fetch_strb_t`

Alias for logic [LogFetchStrbWidth-1:0]

`log_fetch_axil_aw_chan_t`

Packed struct

Table 8. `log_fetch_axil_aw_chan_t`
Field	Type	Description
`addr`	`log_fetch_addr_t`
`prot`	`axi_pkg::prot_t`

`log_fetch_axil_w_chan_t`

Packed struct

Table 9. `log_fetch_axil_w_chan_t`
Field	Type	Description
`data`	`log_fetch_data_t`
`strb`	`log_fetch_strb_t`

`log_fetch_axil_b_chan_t`

Packed struct

Table 10. `log_fetch_axil_b_chan_t`
Field	Type	Description
`resp`	`axi_pkg::resp_t`

`log_fetch_axil_ar_chan_t`

Packed struct

Table 11. `log_fetch_axil_ar_chan_t`
Field	Type	Description
`addr`	`log_fetch_addr_t`
`prot`	`axi_pkg::prot_t`

`log_fetch_axil_r_chan_t`

Packed struct

Table 12. `log_fetch_axil_r_chan_t`
Field	Type	Description
`data`	`log_fetch_data_t`
`resp`	`axi_pkg::resp_t`

`log_fetch_axil_req_t`

Packed struct

Table 13. `log_fetch_axil_req_t`
Field	Type	Description
`aw`	`log_fetch_axil_aw_chan_t`
`aw_valid`	`logic`
`w`	`log_fetch_axil_w_chan_t`
`w_valid`	`logic`
`b_ready`	`logic`
`ar`	`log_fetch_axil_ar_chan_t`
`ar_valid`	`logic`
`r_ready`	`logic`

`log_fetch_axil_resp_t`

Packed struct

Table 14. `log_fetch_axil_resp_t`
Field	Type	Description
`aw_ready`	`logic`
`w_ready`	`logic`
`b`	`log_fetch_axil_b_chan_t`
`b_valid`	`logic`
`ar_ready`	`logic`
`r`	`log_fetch_axil_r_chan_t`
`r_valid`	`logic`

`log_write_addr_t`

Alias for logic [LogWriteAddrWidth-1:0]

`log_write_data_t`

Alias for logic [LogWriteDataWidth-1:0]

`log_write_strb_t`

Alias for logic [LogWriteStrbWidth-1:0]

`log_write_axil_aw_chan_t`

Packed struct

Table 15. `log_write_axil_aw_chan_t`
Field	Type	Description
`addr`	`log_write_addr_t`
`prot`	`axi_pkg::prot_t`

`log_write_axil_w_chan_t`

Packed struct

Table 16. `log_write_axil_w_chan_t`
Field	Type	Description
`data`	`log_write_data_t`
`strb`	`log_write_strb_t`

`log_write_axil_b_chan_t`

Packed struct

Table 17. `log_write_axil_b_chan_t`
Field	Type	Description
`resp`	`axi_pkg::resp_t`

`log_write_axil_ar_chan_t`

Packed struct

Table 18. `log_write_axil_ar_chan_t`
Field	Type	Description
`addr`	`log_write_addr_t`
`prot`	`axi_pkg::prot_t`

`log_write_axil_r_chan_t`

Packed struct

Table 19. `log_write_axil_r_chan_t`
Field	Type	Description
`data`	`log_write_data_t`
`resp`	`axi_pkg::resp_t`

`log_write_axil_req_t`

Packed struct

Table 20. `log_write_axil_req_t`
Field	Type	Description
`aw`	`log_write_axil_aw_chan_t`
`aw_valid`	`logic`
`w`	`log_write_axil_w_chan_t`
`w_valid`	`logic`
`b_ready`	`logic`
`ar`	`log_write_axil_ar_chan_t`
`ar_valid`	`logic`
`r_ready`	`logic`

`log_write_axil_resp_t`

Packed struct

Table 21. `log_write_axil_resp_t`
Field	Type	Description
`aw_ready`	`logic`
`w_ready`	`logic`
`b`	`log_write_axil_b_chan_t`
`b_valid`	`logic`
`ar_ready`	`logic`
`r`	`log_write_axil_r_chan_t`
`r_valid`	`logic`

`log_region_size_t`

Alias for logic [LogRegionSizeW-1:0]

`log_len_t`

Alias for logic [LogLenWidth-1:0]

`log_index_t`

Log fetch parameters

Alias for logic [LogIndexWidth-1:0]

`byte_t`

Log fetch parameters

Alias for logic [7:0]

`log_word_t`

Alias for byte_t [LogWordSize-1:0]

`log_word_byte_ptr_t`

Alias for logic [LogWordBytePtrWidth-1:0]

`log_words_fetched_cnt_t`

Log write parameters

Alias for logic [LogWordsFetchedCntWidth-1:0]

`log_bytes_written_cnt_t`

//////////////////

Alias for logic [LogBytesWrittenCntWidth-1:0]

`log_fetch_fsm_state_e`

//////////////////

Enum (logic [1:0])

Table 22. `log_fetch_fsm_state_e`
Value	Number	Description
`ST_LOG_FETCH_IDLE`	2'd0
`ST_LOG_FETCH_REQ`	2'd1
`ST_LOG_FETCH_WAIT`	2'd2

`log_write_fsm_state_e`

Enum (logic [1:0])

Table 23. `log_write_fsm_state_e`
Value	Number	Description
`ST_LOG_WRITE_IDLE`	2'd0
`ST_LOG_WRITE_REQ`	2'd1
`ST_LOG_WRITE_WAIT`	2'd2

`log_word_floor`

Function returning log_len_t

Table 24. `log_word_floor`
Name	Direction	Type	Description
`byte_count`	input	`log_len_t`