memory_interface
Bridge an AXI memory port onto a memory macro and forward an AXI-Lite CSR port.
The two ports are independent; there is no address decode between them. The memory port subtracts MEM_BASE_ADDR from AW and AR addresses and feeds axi_to_mem with a buffer depth of 1. Every request is accepted at once and the macro must return read data on the clock after the request; mem_req_o carries the clock the macro runs on. With READ_ONLY set, writes are acknowledged but never reach the macro, and mem_req_t needs only the clk, req and addr fields. The CSR port subtracts CSR_BASE_ADDR from AW and AR addresses and forwards all traffic to csr_out_*. busy_o is the axi_to_mem busy status.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
MEM_ADDR_WIDTH | int unsigned | 0 | Memory AXI address width; at most 64. |
MEM_DATA_WIDTH | int unsigned | 0 | Memory AXI and bank data width; one of 32, 64, 128, 256, 512 or 1024. |
MEM_ID_WIDTH | int unsigned | 0 | Memory ID width. |
READ_ONLY | bit | 1'b0 | Never forward writes to the macro. |
CSR_ADDR_WIDTH | int unsigned | 0 | CSR AXI-Lite address width; at most 64. |
CSR_DATA_WIDTH | int unsigned | 0 | Data width of both CSR AXI-Lite ports; 32 or 64. |
CSR_BASE_ADDR | logic [31:0] | 0 | Subtracted from CSR AW and AR addresses; must be aligned to CSR_DATA_WIDTH/8 bytes. |
MEM_BASE_ADDR | logic [31:0] | 0 | Subtracted from memory AW and AR addresses; must be aligned to MEM_DATA_WIDTH/8 bytes. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | logic | System clock. |
rst_ni | input | logic | Async reset, active-low. |
mem_axi_req_i | input | mem_axi_req_t | AXI memory slave request; addresses are offset by MEM_BASE_ADDR before axi_to_mem. |
mem_axi_resp_o | output | mem_axi_resp_t | AXI memory slave response. |
csr_in_axil_req_i | input | csr_axil_req_t | Inbound CSR AXI-Lite request. |
csr_in_axil_resp_o | output | csr_axil_resp_t | Inbound CSR AXI-Lite response. |
csr_out_axil_req_o | output | csr_axil_req_t | csr_in_axil_req_i with CSR_BASE_ADDR subtracted from the AW and AR addresses. |
csr_out_axil_resp_i | input | csr_axil_resp_t | Forwarded CSR AXI-Lite response. |
mem_req_o | output | mem_req_t | Macro request. |
mem_rsp_i | input | mem_rsp_t | Macro read data, returned on the clock after mem_req_o.req. |
busy_o | output | | High while axi_to_mem has a memory-port transaction in progress. |