pwm_wrap
Wrap the OpenTitan PWM and its pad-control register behind one AXI-Lite port.
The AXI-Lite slave is demuxed onto three ports: the PWM register map, the CTRL register map and an error slave that answers DECERR with read data 0xBADCAB1E for every other address. PWM accesses are rebased by subtracting REG_MAP_BASE_ADDR and bridged to the PWM TL-UL port. CTRL.PAD_EN drives pad_en_o, one bit per channel; it does not gate the PWM itself. The demux, the bridge, CTRL, the alert receiver and the PWM register interface run on clk_i; clk_core_i clocks the PWM phase counters and channel outputs. fatal_alert_o aggregates the fatal alert pulse with integ_fail of all alert channels. RACL is compiled out.
The register layout depends on NUM_OUTPUTS. Static assertions check that the generated map handed in through REG_MAP_SIZE and the *_REG_OFFSET parameters matches the layout of the PWM built here, that the generated CTRL.PAD_EN has NUM_OUTPUTS bits, and that both map bases are aligned to their block sizes.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
NUM_OUTPUTS | int unsigned | 4 | Number of PWM channels; 1 to 32. |
REG_MAP_BASE_ADDR | logic [31:0] | '0 | Base address of the PWM registers, subtracted from AW and AR addresses; aligned to the PWM block size. |
REG_MAP_SIZE | logic [31:0] | '0 | Size of the generated PWM register map in bytes. |
CTRL_REG_MAP_BASE_ADDR | logic [31:0] | '0 | Base address of the CTRL register map; aligned to its block size. |
CTRL_REG_MAP_SIZE | logic [31:0] | '0 | Size of the generated CTRL register map in bytes. |
PWM_PARAM_REG_OFFSET | logic [31:0] | '0 | Offset of PWM_PARAM_0 in the generated map. |
DUTY_CYCLE_REG_OFFSET | logic [31:0] | '0 | Offset of DUTY_CYCLE_0 in the generated map. |
BLINK_PARAM_REG_OFFSET | logic [31:0] | '0 | Offset of BLINK_PARAM_0 in the generated map. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | logic | Register interface clock. |
rst_ni | input | logic | Register interface reset, active-low, synchronized to clk_i. |
clk_core_i | input | logic | PWM counter clock; may be asynchronous to clk_i. |
rst_core_ni | input | logic | PWM counter reset, active-low, synchronized to clk_core_i. |
test_en_i | input | logic | DFT test mode to the AXI cells. |
csr_axil_req_i | input | axil_req_t | AXI-Lite slave for the PWM and CTRL registers, at system addresses. |
csr_axil_resp_o | output | axil_resp_t | Response on the register slave. |
pad_en_o | output | logic [NUM_OUTPUTS-1:0] | CTRL.PAD_EN, one bit per channel, on clk_i; resets to 0. |
pwm_o | output | logic [NUM_OUTPUTS-1:0] | PWM channel outputs, from the clk_core_i domain. |
pwm_en_o | output | logic [NUM_OUTPUTS-1:0] | PWM channel output enables, from the clk_core_i domain. |
fatal_alert_o | output | logic | Aggregated fatal alert (alert pulse | integ_fail of all alert channels). |