scrambler_2048x32

Scramble a 2048x32 SRAM with a PRESENT-style round and address tweak.

Implements a simplified, single-round PRESENT-style cipher for 32-bit data blocks with address tweaking. The round_key is the expanded address XORed with scrambler_key_i.

The round depends on BYTE_WISE:

  • BYTE_WISE=0 (full word): scramble is XOR round_key, sbox4 over 8 nibbles, then perm32; descramble is iperm32, ibox4, then XOR round_key.
  • BYTE_WISE=1 (per-byte): scramble ends in perm8 x4; descramble starts with iperm8 x4.

Parameters

Table 1. Parameters
NameTypeDefaultDescription
ADDR_WIDTHint unsigned11SRAM address width. Must be 11: the address scramble is fixed to addr_scramble11.
DATA_WIDTHint unsigned32SRAM data width; only 32-bit is supported.
BYTE_WISEint unsigned0Use per-byte perm8 instead of full-word perm32. 0 applies perm32 to the full word; 1 applies perm8 to each byte lane.

Ports

Table 2. Ports
NameDirectionTypeDescription
addr_iinputlogic [ADDR_WIDTH-1:0]Plaintext SRAM address. Keys both the address scramble and the data round key, so on the read path it must be the address the read data was fetched from.
byte_mask_iinputlogic [DATA_WIDTH/8-1:0]Byte enables; unused in every mode. Reserved for per-byte-lane gating.
scrambler_key_iinputlogic [31:0]32-bit scrambler key. XORed with the expanded address to form the data round key; its low ADDR_WIDTH bits key the address scramble.
scrambled_addr_ooutputlogic [ADDR_WIDTH-1:0]Scrambled address sent to the SRAM macro. Combinational: addr_i XOR the low key bits, S-boxes, then a bit permutation.
write_data_iinputlogic [DATA_WIDTH-1:0]Plaintext write data.
scrambled_write_data_ooutputlogic [DATA_WIDTH-1:0]Scrambled write data. Combinational function of write_data_i, addr_i and the key; stored in the SRAM macro.
scrambled_read_data_iinputlogic [DATA_WIDTH-1:0]Scrambled read data from the SRAM.
read_data_ooutputlogic [DATA_WIDTH-1:0]Descrambled read data. Combinational; descrambled with the round key for addr_i.