uart_16550

Wrap a 16550-compatible UART core and register block behind AXI-Lite.

TX_FIFO_DEPTH and RX_FIFO_DEPTH size the FIFOs. Exposes rx/tx, modem controls (cts/dsr/ri/dcd in, rts/dtr/out1/out2 out), DMA rxrdy/txrdy, err_o, and irq_o. An AXI-Lite demux with one outstanding transaction per channel splits the bus over three register maps: while LCR.DLAB is set, DLL and DLM go to the divisor-latch map; writes to THR and FCR go to the write-only map; everything else goes to the main map. In MCR.LOOP system loopback the modem outputs are held high, and in MCR.LINE_LOOPBACK rts_no, dtr_no, out1_no and out2_no follow cts_ni, dsr_ni, ri_ni and dcd_ni.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`TX_FIFO_DEPTH`	`int unsigned`	`16`	Transmit FIFO depth in characters. Must be a power of 2 from 4 to 4096 inclusive.
`RX_FIFO_DEPTH`	`int unsigned`	`16`	Receive FIFO depth in characters. Must be a power of 2 from 4 to 4096 inclusive.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock, rising-edge triggered.
`rst_ni`	input	`logic`	Active-low reset. Assert asynchronously; deassert synchronously to clk_i. Resets all registers to their defaults and clears the FIFOs.
`axil_req_i`	input	`axil_req_t`	AXI-Lite req (AXI4-Lite Register Interface).
`axil_resp_o`	output	`axil_resp_t`	AXI-Lite resp.
`rx_i`	input	`logic`	Serial receive line; idles high. Asynchronous; synchronized internally.
`tx_o`	output	`logic`	Serial transmit line; idles high.
`cts_ni`	input	`logic`	Clear To Send, active-low (Modem Interface). Asynchronous; synchronized internally. Reported in MSR.CTS; a change sets MSR.DCTS and raises the modem status interrupt. Does not stall the transmitter.
`dsr_ni`	input	`logic`	Data Set Ready, active-low. Asynchronous; synchronized internally. Reported in MSR.DSR; a change sets MSR.DDSR.
`ri_ni`	input	`logic`	Ring Indicator, active-low. Asynchronous; synchronized internally. Reported in MSR.RI; a trailing edge sets MSR.TERI.
`dcd_ni`	input	`logic`	Data Carrier Detect, active-low. Asynchronous; synchronized internally. Reported in MSR.DCD; a change sets MSR.DDCD.
`rts_no`	output	`logic`	Request To Send, active-low; driven from MCR.RTS outside loopback. The receiver never deasserts it on its own when the RX FIFO fills.
`dtr_no`	output	`logic`	Data Terminal Ready, active-low; driven from MCR.DTR.
`out1_no`	output	`logic`	General-purpose output 1, active-low; driven from MCR.OUT1.
`out2_no`	output	`logic`	General-purpose output 2, active-low; driven from MCR.OUT2.
`rxrdy_o`	output	`logic`	Receiver ready, active-high (DMA Interface). FCR.DMA_MODE_SELECT chooses mode 0 or mode 1 signalling.
`txrdy_o`	output	`logic`	Transmitter ready, active-high. FCR.DMA_MODE_SELECT chooses mode 0 or mode 1 signalling.
`err_o`	output	`logic`	Storage integrity error, active-high: a data parity or pointer error in the TX or RX FIFO, or a parity error in the non-FIFO holding register. Unrelated to the parity of received characters.
`irq_o`	output	`logic`	Interrupt request, active-high. High while any of the six enabled interrupt sources is pending.