uart_core

Bind 16550 TX/RX datapaths, FIFOs, modem status, and interrupts to the register structs.

TX_FIFO_DEPTH and RX_FIFO_DEPTH size the FIFOs; localparams derive baud, FIFO depth/threshold, timeout, and trigger-level types. reg_out_i/reg_in_o are the generated register HW outputs and inputs. Exposes serial, modem, DMA ready, err_o, and irq_o. A zero divisor latch (DLM:DLL) disables both the transmitter and the receiver.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`TX_FIFO_DEPTH`	`int unsigned`	`16`	Transmit FIFO depth. In uart_16550, a power of 2 from 4 to 4096.
`RX_FIFO_DEPTH`	`int unsigned`	`16`	Receive FIFO depth. In uart_16550, a power of 2 from 4 to 4096.
`BaudCntWidth`	`int unsigned`	`16`	Baud-rate divider counter width.
`RxFifoDepthWidth`	`int unsigned`	`$clog2(RX_FIFO_DEPTH + 1)`	Bits to hold an RX FIFO fill level of 0 to RX_FIFO_DEPTH.
`RxFifoThresholdWidth`	`int unsigned`	`$clog2(4096 + 1)`	Bits to hold the largest RX trigger level, 4096 entries.
`TimeoutCntWidth`	`int unsigned`	`$clog2(MaxFrameLen * TimeoutCharCnt)`	Bits to count baud ticks over four maximum-length frames.
`TriggerLevelWidth`	`int unsigned`	`$clog2(NumTriggerLevels)`	Bits to encode one of the RX trigger levels.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset.
`reg_out_i`	input	`uart_16550_reg_out_t`	Software-programmed register fields from the generated register block.
`reg_in_o`	output	`uart_16550_reg_in_t`	Hardware-driven inputs to the generated register block.
`rx_i`	input	`logic`	Asynchronous; two-flop synchronized and 3-sample majority filtered. Ignored in system or line loopback.
`tx_o`	output	`logic`	Registered; low during a set break. Held high in system loopback and equal to rx_i in line loopback.
`cts_ni`	input	`logic`	Clear To Send, active-low; synchronized into MSR. Drives rts_no in line loopback.
`dsr_ni`	input	`logic`	Data Set Ready, active-low; synchronized into MSR. Drives dtr_no in line loopback.
`ri_ni`	input	`logic`	Ring Indicator, active-low; synchronized into MSR. Drives out1_no in line loopback.
`dcd_ni`	input	`logic`	Data Carrier Detect, active-low; synchronized into MSR. Drives out2_no in line loopback.
`rts_no`	output	`logic`	Request To Send, active-low; the inverted MCR RTS bit, high in system loopback.
`dtr_no`	output	`logic`	Data Terminal Ready, active-low; the inverted MCR DTR bit, high in system loopback.
`out1_no`	output	`logic`	Inverted MCR OUT1 bit, active-low; high in system loopback.
`out2_no`	output	`logic`	Inverted MCR OUT2 bit, active-low; high in system loopback.
`rxrdy_o`	output	`logic`	Active-high DMA receive request: in mode 0 while the RX FIFO is not empty; in mode 1 from the trigger level or a character timeout until the FIFO empties.
`txrdy_o`	output	`logic`	Active-high DMA transmit request: in mode 0 while the TX FIFO is empty; in mode 1 until it fills, then again once it drains.
`err_o`	output	`logic`	High on a data-parity or pointer integrity error in the TX or RX FIFO, or a parity error in the holding register used in non-FIFO mode.
`irq_o`	output	`logic`	Interrupt request, active-high; the OR of the enabled interrupt sources.