uart_rx

Sample rx_i at 16× baud and assemble a UART receive frame.

tick_baud_x16_i paces oversampling; word_length_i, parity_enable_i, parity_odd_i, and extra_stop_bit_i shape the expected frame. rx_valid_o pulses with rx_data_o; frame_err_o and rx_parity_err_o report framing and parity faults with the same pulse. rx_i is not synchronized here; uart_core synchronizes and filters it. A start bit that is no longer low at mid-bit is discarded as a glitch.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset.
`rx_enable_i`	input	`logic`	Low clears the receiver and holds it idle.
`tick_baud_x16_i`	input	`logic`	16× baud oversample tick.
`parity_enable_i`	input	`logic`	Include a parity bit in the frame.
`parity_odd_i`	input	`logic`	1 selects odd parity; 0 selects even.
`parity_force_i`	input	`logic`	Stick parity. When set with parity_enable_i, the check flags data with an odd number of ones and ignores the received parity bit.
`word_length_i`	input	`logic [3:0]`	Data bits per frame.
`extra_stop_bit_i`	input	`logic`	Add a second stop bit when high.
`tick_baud_o`	output	`logic`	One-cycle pulse per bit period from the receive baud divider, realigned to mid-bit at each start bit.
`rx_valid_o`	output	`logic`	One-cycle pulse at the end of each received frame.
`rx_data_o`	output	`logic [7:0]`	Received data, valid with rx_valid_o.
`idle_o`	output	`logic`	High when no frame is being received or rx_enable_i is low.
`frame_err_o`	output	`logic`	Pulses with rx_valid_o when a stop bit is sampled low. Two stop bits are checked when extra_stop_bit_i is set and the word length is not 5.
`rx_parity_err_o`	output	`logic`	Pulses with rx_valid_o when parity_enable_i is set and the parity check fails.
`rx_i`	input	`logic`	Serial receive line.