uart_tx

Serialize wr_data_i onto tx_o at the baud tick rate. A frame is a low start bit, the data bits LSB first, the optional parity bit and high stop bits; the baud tick is every sixteenth tick_baud_x16_i.

wr_i loads a frame from wr_data_i and wr_parity_i using word_length_i, parity_enable_i, and extra_stop_bit_i. tick_baud_x16_i derives the baud tick; idle_o is high when the shifter is empty or tx_enable_i is low.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Async reset, active-low.
`tx_enable_i`	input	`logic`	Transmitter enable. Low clears the shifter and holds tx_o high.
`tick_baud_x16_i`	input	`logic`	16× baud oversample tick.
`parity_enable_i`	input	`logic`	Include a parity bit in the frame.
`word_length_i`	input	`logic [3:0]`	Data bits per frame, 5 to 8.
`extra_stop_bit_i`	input	`logic`	Add a second stop bit when high.
`wr_i`	input	`logic`	Pulse that loads wr_data_i into the shifter. A load while busy replaces the frame in progress, so assert it only while idle_o is high.
`wr_parity_i`	input	`logic`	Parity bit loaded with wr_data_i; used only when parity_enable_i is high.
`wr_data_i`	input	`logic [7:0]`	Transmit data byte.
`idle_o`	output	`logic`	High when the shifter is empty or tx_enable_i is low.
`tx_o`	output	`logic`	Serial transmit line; registered, idles high.