uart_log_engine_wrap

Map one uart_16550, an optional log engine and a CTRL register behind one AXI-Lite port.

Decodes the UART, log-engine and CTRL windows set by the *_REG_MAP_* parameters. Addresses outside every window go to an error slave that answers DECERR with read data 0xBADCAB1E. The log engine shares the UART register port with the CSR path through an AXI-Lite mux and is paced by uart_txrdy_o. UART serial, modem, DMA and interrupt pins pass to the top unchanged.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`UART_TX_FIFO_DEPTH`	`int unsigned`	`32`	Per-UART TX FIFO depth. Must be a power of 2 from 4 to 4096 inclusive.
`UART_RX_FIFO_DEPTH`	`int unsigned`	`32`	Per-UART RX FIFO depth. Must be a power of 2 from 4 to 4096 inclusive.
`GEN_LOG_ENGINE`	`bit`	`1'b1`	Instantiates the log engine when set. When clear, the log-engine window is not decoded, log_fetch_axil_req_o is idle and log_engine_irq_o is low.
`LOG_ENGINE_FIFO_DEPTH`	`int unsigned`	`32`	Entries in the log engine's read-data FIFO between log fetch and UART write.
`UART_REG_MAP_BASE_ADDR`	`bit [RegAddrWidth-1:0]`	`0`	UART register-map base.
`UART_REG_MAP_SIZE`	`bit [RegAddrWidth-1:0]`	`0`	UART register-map size.
`LOG_ENGINE_REG_MAP_BASE_ADDR`	`bit [RegAddrWidth-1:0]`	`0`	Log-engine register-map base.
`LOG_ENGINE_REG_MAP_SIZE`	`bit [RegAddrWidth-1:0]`	`0`	Log-engine register-map size.
`UART_LOG_ENGINE_CTRL_REG_MAP_BASE_ADDR`	`bit [RegAddrWidth-1:0]`	`0`	Log-engine CTRL base.
`UART_LOG_ENGINE_CTRL_REG_MAP_SIZE`	`bit [RegAddrWidth-1:0]`	`0`	Log-engine CTRL size.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock, rising-edge triggered.
`rst_ni`	input	`logic`	Active-low reset. Assert asynchronously; deassert synchronously to clk_i.
`csr_axil_req_i`	input	`csr_axil_req_t`	Register-port request, decoded onto the UART, log-engine and CTRL maps.
`csr_axil_resp_o`	output	`csr_axil_resp_t`	Csr AXI-Lite resp.
`log_fetch_axil_req_o`	output	`log_engine_pkg::log_fetch_axil_req_t`	Log-engine log-fetch request; all zero when GEN_LOG_ENGINE is clear.
`log_fetch_axil_resp_i`	input	`log_engine_pkg::log_fetch_axil_resp_t`	Log fetch AXI-Lite resp.
`uart_en_o`	output	`logic`	Uart en, active-high (Control Interface); driven from CTRL.UART_EN.
`uart_rx_i`	input	`logic`	Uart rx (UART Interface); idles high. Asynchronous; synchronized internally.
`uart_tx_o`	output	`logic`	Uart tx; idles high.
`uart_cts_ni`	input	`logic`	uart cts, active-low (UART Modem Interface). Asynchronous; synchronized internally.
`uart_dsr_ni`	input	`logic`	uart dsr, active-low. Asynchronous; synchronized internally.
`uart_ri_ni`	input	`logic`	uart ri, active-low. Asynchronous; synchronized internally.
`uart_dcd_ni`	input	`logic`	uart dcd, active-low. Asynchronous; synchronized internally.
`uart_rts_no`	output	`logic`	uart rts, active-low.
`uart_dtr_no`	output	`logic`	uart dtr, active-low.
`uart_out1_no`	output	`logic`	uart out1, active-low.
`uart_out2_no`	output	`logic`	uart out2, active-low.
`uart_rxrdy_o`	output	`logic`	Uart rxrdy, active-high (UART DMA Interface): in mode 0 while the RX FIFO is not empty; in mode 1 from the trigger level or a character timeout until the FIFO empties.
`uart_txrdy_o`	output	`logic`	Uart txrdy, active-high: in mode 0 while the TX FIFO is empty; in mode 1 until it fills, then again once it drains. Also paces the log engine.
`uart_err_o`	output	`logic`	Uart err, active-high (UART Error Interface). Flags a data-parity or pointer integrity error in the UART FIFOs or holding registers, unrelated to the parity of received characters.
`uart_irq_o`	output	`logic`	Uart irq, active-high (Interrupt Interface); the OR of the enabled UART interrupt sources.
`log_engine_irq_o`	output	`logic`	Log engine irq, active-high; low when GEN_LOG_ENGINE is clear.