uart_log_engine_wrap_pkg

Define register-map selects and AXI-Lite typedefs for the UART plus log-engine wrap.

Defines the 32-bit csr_axil types and uart_log_engine_wrap_reg_map_e, which selects the UART, log-engine, CTRL or undefined register map.

`reg_addr_t`

Alias for logic [RegAddrWidth-1:0]

Alias for logic [RegDataWidth-1:0]

Alias for logic [RegStrbWidth-1:0]

Packed struct

Table 1. `csr_axil_aw_chan_t`
Field	Type	Description
`addr`	`reg_addr_t`
`prot`	`axi_pkg::prot_t`

Packed struct

Table 2. `csr_axil_w_chan_t`
Field	Type	Description
`data`	`reg_data_t`
`strb`	`reg_strb_t`

Packed struct

Table 3. `csr_axil_b_chan_t`
Field	Type	Description
`resp`	`axi_pkg::resp_t`

Packed struct

Table 4. `csr_axil_ar_chan_t`
Field	Type	Description
`addr`	`reg_addr_t`
`prot`	`axi_pkg::prot_t`

Packed struct

Table 5. `csr_axil_r_chan_t`
Field	Type	Description
`data`	`reg_data_t`
`resp`	`axi_pkg::resp_t`

Packed struct

Packed struct

Enum (logic [$clog2( NumRegMaps )-1:0])