uart_wrap

Map NUM_UARTS uart_log_engine_wrap instances behind one AXI-Lite port.

Instance i owns the window at UART_LOG_ENGINE_WRAP_0__REG_MAP_BASE_ADDR plus i*UART_LOG_ENGINE_WRAP_SPACING; its UART, log-engine and CTRL bases shift by the same amount. Addresses outside every window go to an error slave that answers DECERR with read data 0xBADCAB1E. The instances' log-fetch masters share log_fetch_axil_* through an AXI-Lite mux. All other outputs are per-instance vectors, bit i from instance i.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NUM_UARTS`	`int unsigned`	`4`	UART instance count; 1 to MaxNumUarts.
`UART_TX_FIFO_DEPTH`	`int unsigned`	`32`	Per-UART TX FIFO depth.
`UART_RX_FIFO_DEPTH`	`int unsigned`	`32`	Per-UART RX FIFO depth.
`GEN_LOG_ENGINES`	`bit [NUM_UARTS-1:0]`	`{NUM_UARTS{1'b1}}`	Bit i instantiates the log engine of UART i.
`LOG_ENGINE_FIFO_DEPTH`	`int unsigned`	`4`	Entries in each log engine's read-data FIFO.
`UART_LOG_ENGINE_WRAP_0__REG_MAP_BASE_ADDR`	`bit [uart_wrap_pkg::RegAddrWidth-1:0]`	`0`	Base of instance 0's decode window.
`UART_LOG_ENGINE_WRAP_0__REG_MAP_SIZE`	`bit [uart_wrap_pkg::RegAddrWidth-1:0]`	`0`	Size of each instance's decode window.
`UART_LOG_ENGINE_WRAP_SPACING`	`bit [uart_wrap_pkg::RegAddrWidth-1:0]`	`0`	Address stride between instance windows and their internal map bases.
`UART_REG_MAP_BASE_ADDR`	`bit [uart_wrap_pkg::RegAddrWidth-1:0]`	`0`	Instance 0's UART register-map base.
`UART_REG_MAP_SIZE`	`bit [uart_wrap_pkg::RegAddrWidth-1:0]`	`0`	Per-instance UART register-map size.
`LOG_ENGINE_REG_MAP_BASE_ADDR`	`bit [uart_wrap_pkg::RegAddrWidth-1:0]`	`0`	Instance 0's log-engine register-map base.
`LOG_ENGINE_REG_MAP_SIZE`	`bit [uart_wrap_pkg::RegAddrWidth-1:0]`	`0`	Per-instance log-engine register-map size.
`UART_LOG_ENGINE_CTRL_REG_MAP_BASE_ADDR`	`bit [uart_wrap_pkg::RegAddrWidth-1:0]`	`0`	Instance 0's CTRL register-map base.
`UART_LOG_ENGINE_CTRL_REG_MAP_SIZE`	`bit [uart_wrap_pkg::RegAddrWidth-1:0]`	`0`	Per-instance CTRL register-map size.
`NumRegMaps`	`int unsigned`	`NUM_UARTS + 1`	+1 for error slave.
`UndefinedRegMap`	`uart_wrap_reg_map_select_t`	`uart_wrap_reg_map_select_t'(NumRegMaps - 1)`	Unmapped address sink select.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset.
`csr_axil_req_i`	input	`uart_wrap_pkg::csr_axil_req_t`	Register-port request, decoded onto the instance windows.
`csr_axil_resp_o`	output	`uart_wrap_pkg::csr_axil_resp_t`	Csr AXI-Lite resp.
`log_fetch_axil_req_o`	output	`log_engine_pkg::log_fetch_axil_req_t`	Log-fetch request muxed from every instance's log engine.
`log_fetch_axil_resp_i`	input	`log_engine_pkg::log_fetch_axil_resp_t`	Log fetch AXI-Lite resp.
`uart_en_o`	output	`logic [NUM_UARTS-1:0]`	Per-UART CTRL.UART_EN value, active-high; not used inside the wrapper.
`uart_rx_i`	input	`logic [NUM_UARTS-1:0]`	Per-UART serial receive data; asynchronous, synchronized in uart_core.
`uart_tx_o`	output	`logic [NUM_UARTS-1:0]`	Serial transmit data to the pad, one bit per UART; idles high.
`uart_cts_ni`	input	`logic [NUM_UARTS-1:0]`	uart cts, active-low (UART Modem Interface).
`uart_dsr_ni`	input	`logic [NUM_UARTS-1:0]`	uart dsr, active-low.
`uart_ri_ni`	input	`logic [NUM_UARTS-1:0]`	uart ri, active-low.
`uart_dcd_ni`	input	`logic [NUM_UARTS-1:0]`	uart dcd, active-low.
`uart_rts_no`	output	`logic [NUM_UARTS-1:0]`	uart rts, active-low.
`uart_dtr_no`	output	`logic [NUM_UARTS-1:0]`	uart dtr, active-low.
`uart_out1_no`	output	`logic [NUM_UARTS-1:0]`	uart out1, active-low.
`uart_out2_no`	output	`logic [NUM_UARTS-1:0]`	uart out2, active-low.
`uart_rxrdy_o`	output	`logic [NUM_UARTS-1:0]`	Per-UART DMA receive request, active-high: in mode 0 while the RX FIFO is not empty; in mode 1 from the trigger level or a character timeout until the FIFO empties.
`uart_txrdy_o`	output	`logic [NUM_UARTS-1:0]`	Per-UART DMA transmit request, active-high: in mode 0 while the TX FIFO is empty; in mode 1 until it fills, then again once it drains.
`uart_err_o`	output	`logic [NUM_UARTS-1:0]`	Per-UART FIFO or holding-register integrity error, active-high.
`uart_irq_o`	output	`logic [NUM_UARTS-1:0]`	Per-UART interrupt request, active-high.
`log_engine_irq_o`	output	`logic [NUM_UARTS-1:0]`	Per-UART log-engine interrupt, active-high; low for a UART generated without a log engine.