zeroer

Write zeros over a programmed AXI address range from a ctrl port.

zeroer_ctrl_axi_* programs DEST_ADDR and SIZE in bytes, and a write to CTRL_STATUS starts the clear unless SIZE is 0; mst_axi_* performs the clears. The clears are INCR write bursts of zeros at full data width, with ID 0, at most 256 beats, never crossing a 4 KiB boundary, and strobes limited to the range. The master never reads and ignores write response codes. An illegal FSM state locks the zeroer busy until reset. With cg_enable_i high, the clear FSM clock runs only while busy and the register clock is gated after ctrl-bus inactivity; zeroer_intp_o signals completion.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`CTRL_ADDR_WIDTH`	`int unsigned`	`5`	Ctrl AXI address width.
`CTRL_DATA_WIDTH`	`int unsigned`	`64`	Ctrl AXI data width.
`CTRL_ID_WIDTH`	`int unsigned`	`8`	Ctrl AXI ID width.
`CTRL_USER_WIDTH`	`int unsigned`	`12`	Ctrl AXI user width.
`AXI_ADDR_WIDTH`	`int unsigned`	`56`	Master AXI address width; DEST_ADDR is truncated to it.
`AXI_DATA_WIDTH`	`int unsigned`	`64`	Master AXI data width.
`AXI_USER_WIDTH`	`int unsigned`	`12`	Master AXI user width.
`MST_ID_WIDTH`	`int unsigned`	`3`	Master AXI ID width.
`CG_HYSTERESIS_W`	`int unsigned`	`6`	Clock-gater hysteresis width.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock; source of both gated clocks.
`rst_ni`	input	`logic`	Async reset, active-low.
`test_en_i`	input	`logic`	DFT test enable; forces both clock gates open.
`cg_enable_i`	input	`logic`	Enable gating of the clear FSM and register clocks.
`cg_hysteresis_i`	input	`logic [CG_HYSTERESIS_W-1:0]`	Idle cycles before gating the register clock.
`zeroer_busy_o`	output	`logic`	Zeroer has work in flight: a start, an active clear, or writes awaiting a response. Also high in the error state.
`zeroer_intp_o`	output	`logic`	Completion interrupt: a one-cycle pulse when busy falls, if CTRL_STATUS.INT_EN is set.
`zeroer_ctrl_axi_req_i`	input	`zeroer_ctrl_req_t`	Ctrl AXI slave request.
`zeroer_ctrl_axi_resp_o`	output	`zeroer_ctrl_resp_t`	Ctrl AXI slave response.
`mst_axi_req_o`	output	`mst_req_t`	Clearing AXI master request.
`mst_axi_resp_i`	input	`mst_resp_t`	Clearing AXI master response.
`zeroer_clk_active_o`	output	`logic`	Register clock is running.
`zeroer_bus_active_o`	output	`logic`	Ctrl bus has a transaction in progress.