dtp

Integrate JTAG, debug STAPs, and the cross-trigger network.

Instantiate jtag_intf_unit, which holds the primary TAP, optional boundary-scan and STAP paths, JTAG2AXI debug ports and IC_RESET TDR slices, and cross_trigger_network, which holds the cross-trigger matrix with CTP pad connections and the AXI-Lite CSRs. dbg_disable_i applies per-TAP debug/test disables from the SEP lifecycle controller. Unused STAP or scan ports must be tied off or looped back as noted on each port.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`JTAG_BSR_ENABLE`	`bit`	`1`	Enable all mandatory JTAG boundary-scan instructions.
`JTAG_EXTEST_TRAIN_ENABLE`	`bit`	`1`	Enable optional JTAG EXTEST_TRAIN instruction.
`JTAG_EXTEST_PULSE_ENABLE`	`bit`	`1`	Enable optional JTAG EXTEST_PULSE instruction.
`JTAG_INTEST_ENABLE`	`bit`	`1`	Enable optional JTAG INTEST instruction.
`JTAG_CLAMP_ENABLE`	`bit`	`1`	Enable optional JTAG CLAMP instruction.
`JTAG_HIGHZ_ENABLE`	`bit`	`1`	Enable optional JTAG HIGHZ instruction.
`JTAG_RUNBIST_ENABLE`	`bit`	`1`	Enable optional JTAG RUNBIST instruction.
`JTAG_TMP_ENABLE`	`bit`	`1`	Enable TMP controller functionality and instructions.
`JTAG_IC_RESET_SMC_ENABLE`	`bit`	`1`	Enable the SMC slice of the IC_RESET TDR.
`JTAG_IC_RESET_EXT_ENABLE`	`bit`	`1`	Enable the external slice of the IC_RESET TDR.
`JTAG_SMC_DBG_ENABLE`	`bit`	`1`	Enable optional JTAG2AXI ports for the SMC debug interface.
`JTAG_STAP_IO_ENABLE`	`bit`	`1`	Enable the STAP for chiplet-to-chiplet connectivity.
`JTAG_IC_RESET_SEP_ENABLE`	`int unsigned`	`1`	Bit 0 enables the SEP slice of the IC_RESET TDR. int unsigned so SpyGlass elaborate -param can override it; in smu it follows CFG.SEP.
`JTAG_SEP_DBG_ENABLE`	`int unsigned`	`1`	Bit 0 enables the SEP debug STAP and the JTAG2AXI bridge to the SEP OTP. int unsigned so SpyGlass elaborate -param can override it; in smu it follows CFG.SEP.
`JTAG_NUM_EXTRA_STAPS`	`int unsigned`	`1`	Number of additional STAPs for local connectivity.
`JTAG_IDCODE_MFR_ID`	`logic [10:0]`	`11'h000`	JTAG IDCODE manufacturer ID.
`JTAG_IDCODE_PART_NUM`	`logic [15:0]`	`16'h0000`	JTAG IDCODE part number.
`JTAG_IDCODE_SI_REV`	`logic [3:0]`	`4'h0`	JTAG IDCODE silicon revision.
`JTAG_OCH_VER`	`logic [7:0]`	`8'h00`	DTP IP major version number reported in JTAG_CAPS.
`JtagNumExtraStapPorts`	`int unsigned`	`(JTAG_NUM_EXTRA_STAPS > 0) ? JTAG_NUM_EXTRA_STAPS : 1`	Extra STAP port count; at least one for tie-off.
`XTRIG_NUM_CTP`	`int unsigned`	`dtp_pkg::DefaultNumCtp`	Number of external cross-trigger ports.
`XTRIG_NUM_INT_CT`	`int unsigned`	`dtp_pkg::DefaultNumIntCt`	Number of internal cross-trigger interfaces.
`XTRIG_NUM_CLK_STOP_REQ`	`int unsigned`	`dtp_pkg::DefaultNumClkStopReq`	Number of clock-stop request inputs.
`XTRIG_INT_CT_MODE`	`logic [XTRIG_NUM_INT_CT-1:0]`	`'0`	Per-lane CTM protocol: 0 = pulse sync (ack unused), 1 = req/ack handshake.
`SMC_OTP_RD_PL_DEPTH`	`logic [1:0]`	`2'h3`	SMC OTP read pipeline depth; 0 = single outstanding.
`SMC_OTP_WR_PL_DEPTH`	`logic [1:0]`	`2'h3`	SMC OTP write pipeline depth; 0 = single outstanding.
`SEP_OTP_RD_PL_DEPTH`	`logic [1:0]`	`2'h3`	SEP OTP read pipeline depth; 0 = single outstanding.
`SEP_OTP_WR_PL_DEPTH`	`logic [1:0]`	`2'h3`	SEP OTP write pipeline depth; 0 = single outstanding.
`SMC_RD_PL_DEPTH`	`logic [1:0]`	`2'h3`	SMC fabric read pipeline depth; 0 = single outstanding.
`SMC_WR_PL_DEPTH`	`logic [1:0]`	`2'h3`	SMC fabric write pipeline depth; 0 = single outstanding.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock for non-JTAG logic.
`rst_n_i`	input	`logic`	Active-low reset for non-JTAG logic.
`pwr_on_rst_ni`	input	`logic`	Power-on reset for JTAG logic, active-low.
`dbg_disable_i`	input	`sep_lifecycle_ctrl_pkg::dbg_disable_t`	Per-TAP debug/test disables from SEP lifecycle; active-high, synchronized to TCK inside.
`jtag_ptap_client_tap_ctrl_i`	input	`jtag_tap_ctrl_t`	Primary JTAG TAP control.
`jtag_ptap_client_tdi_i`	input	`logic`	Primary JTAG TAP TDI.
`jtag_ptap_client_tdo_o`	output	`logic`	Primary JTAG TAP TDO.
`jtag_ptap_client_tdo_oen_o`	output	`logic`	Primary JTAG TAP TDO output enable.
`jtag_bsr_host_scan_ctrl_o`	output	`jtag_scan_ctrl_t`	Boundary-scan host scan control Tie scan in to scan out if JTAG_BSR_ENABLE is clear.
`jtag_bsr_host_scan_in_i`	input	`logic`	Boundary-scan chain input.
`jtag_bsr_host_scan_out_o`	output	`logic`	Boundary-scan chain output.
`jtag_stap_io_host_tap_ctrl_o`	output	`jtag_tap_ctrl_t`	I/O STAP host TAP control (chiplet-to-chiplet) Tie off with 0 if JTAG_STAP_IO_ENABLE is not enabled.
`jtag_stap_io_host_tdi_i`	input	`logic`	I/O STAP TDI.
`jtag_stap_io_host_tdo_o`	output	`logic`	I/O STAP TDO.
`jtag_stap_io_host_tdo_oen_o`	output	`logic`	I/O STAP TDO output enable.
`jtag_stap_smc_host_tap_ctrl_o`	output	`jtag_tap_ctrl_t`	SMC debug STAP host TAP control Tie off with 0 if JTAG_SMC_DBG_ENABLE is not enabled.
`jtag_stap_smc_host_tdi_i`	input	`logic`	SMC debug STAP TDI.
`jtag_stap_smc_host_tdo_o`	output	`logic`	SMC debug STAP TDO.
`jtag_stap_smc_host_tdo_oen_o`	output	`logic`	SMC debug STAP TDO output enable.
`jtag_stap_sep_host_tap_ctrl_o`	output	`jtag_tap_ctrl_t`	SEP debug STAP host TAP control Tie off with 0 if JTAG_SEP_DBG_ENABLE is not enabled.
`jtag_stap_sep_host_tdi_i`	input	`logic`	SEP debug STAP TDI.
`jtag_stap_sep_host_tdo_o`	output	`logic`	SEP debug STAP TDO.
`jtag_stap_sep_host_tdo_oen_o`	output	`logic`	SEP debug STAP TDO output enable.
`jtag_stap_extra_host_tap_ctrl_o`	output	`jtag_tap_ctrl_t`	Extra STAP host TAP controls Tie off with 0 if JTAG_NUM_EXTRA_STAPS == 0.
`jtag_stap_extra_host_tdi_i`	input	`logic`	Extra STAP TDI bits.
`jtag_stap_extra_host_tdo_o`	output	`logic`	Extra STAP TDO bits.
`jtag_stap_extra_host_tdo_oen_o`	output	`logic`	Extra STAP TDO output enables.
`jtag_stap_host_scan_ctrl_o`	output	`jtag_scan_ctrl_t`	Extended STAP scan control Tie scan in to scan out if unused.
`jtag_stap_host_scan_in_i`	input	`logic`	Extended STAP scan input.
`jtag_stap_host_scan_out_o`	output	`logic`	Extended STAP scan output.
`jtag_dfd_host_scan_ctrl_o`	output	`jtag_scan_ctrl_t`	External DFD iJTAG scan control Tie scan in to scan out if unused.
`jtag_dfd_host_scan_in_i`	input	`logic`	DFD iJTAG scan input.
`jtag_dfd_host_scan_out_o`	output	`logic`	DFD iJTAG scan output.
`jtag_dft_secure_host_scan_ctrl_o`	output	`jtag_scan_ctrl_t`	Secure DFT iJTAG scan control Tie scan in to scan out if unused.
`jtag_dft_secure_host_scan_in_i`	input	`logic`	Secure DFT iJTAG scan input.
`jtag_dft_secure_host_scan_out_o`	output	`logic`	Secure DFT iJTAG scan output.
`jtag_dft_host_scan_ctrl_o`	output	`jtag_scan_ctrl_t`	Non-secure DFT iJTAG scan control Tie scan in to scan out if unused.
`jtag_dft_host_scan_in_i`	input	`logic`	Non-secure DFT iJTAG scan input.
`jtag_dft_host_scan_out_o`	output	`logic`	Non-secure DFT iJTAG scan output.
`axi_smc_dbg_req_o`	output	`smc_jtag_axi_req_t`	SMC fabric debug AXI manager request Tie off with 0 if JTAG_SMC_DBG_ENABLE is not enabled.
`axi_smc_dbg_resp_i`	input	`smc_jtag_axi_resp_t`	SMC fabric debug AXI manager response.
`axil_smc_otp_jtag_req_o`	output	`smc_otp_axil_req_t`	SMC OTP debug AXI-Lite manager request Tie off with 0 if JTAG_SMC_DBG_ENABLE is not enabled.
`axil_smc_otp_jtag_resp_i`	input	`smc_otp_axil_resp_t`	SMC OTP debug AXI-Lite manager response.
`axil_sep_otp_jtag_req_o`	output	`sep_otp_axil_req_t`	SEP OTP debug AXI-Lite manager request Tie off with 0 if JTAG_SEP_DBG_ENABLE is not enabled.
`axil_sep_otp_jtag_resp_i`	input	`sep_otp_axil_resp_t`	SEP OTP debug AXI-Lite manager response.
`stop_clks_o`	output	`logic`	Registered OR of the DEBUG_CONTROL clock stop and xtrig_clk_stop_req_i.
`cla_clock_stop_en_o`	output	`logic`	CLA clock-stop enable from DEBUG_CONTROL.
`jtag_boot_stall_ovrd_o`	output	`logic`	Give the JTAG interface control over boot stall.
`jtag_boot_stall_o`	output	`logic`	Cause a boot stall when jtag_boot_stall_ovrd_o is asserted.
`jtag_ic_reset_smc_o`	output	`ic_reset_smc_t`	SMC IC_RESET TDR slice (closest to TDI).
`jtag_ic_reset_sep_o`	output	`ic_reset_sep_t`	SEP IC_RESET TDR slice (middle of the TDR).
`jtag_ic_reset_ext_o`	output	`ic_reset_ext_t`	External IC_RESET TDR slice (closest to TDO).
`jtag_ptap_state_o`	output	`tap_state_e`	Current primary TAP FSM state.
`jtag_ptap_inst_decoded_o`	output	`jtag_instruction_decoded_e`	Current primary TAP instruction (decoded).
`axil_xtrig_req_i`	input	`xtrig_axil_req_t`	Cross-trigger CSR AXI-Lite subordinate request.
`axil_xtrig_resp_o`	output	`xtrig_axil_resp_t`	Cross-trigger CSR AXI-Lite subordinate response.
`xtrig_ctm_src_req_o`	output	`logic [XTRIG_NUM_INT_CT-1:0]`	CTM source requests toward sinks (e.g. CLA) Ack unused when the corresponding mode bit is 0 (pulse sync).
`xtrig_ctm_src_ack_i`	input	`logic [XTRIG_NUM_INT_CT-1:0]`	Acks for CTM-sourced requests Unused in pulse-synchronization mode.
`xtrig_ctm_dst_req_i`	input	`logic [XTRIG_NUM_INT_CT-1:0]`	CTM destination requests from sources (e.g. CLA).
`xtrig_ctm_dst_ack_o`	output	`logic [XTRIG_NUM_INT_CT-1:0]`	Acks for CTM-destined requests Unused in pulse-synchronization mode.
`xtrig_clk_stop_req_i`	input	`logic [XTRIG_NUM_CLK_STOP_REQ-1:0]`	CLA or other device requests to stop the clocks.
`xtrig_ctp_req_out_dout_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP req-out pad data; connect to the GPIO pad ring.
`xtrig_ctp_req_out_dout_en_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP req-out pad output enable.
`xtrig_ctp_req_out_din_i`	input	`logic [XTRIG_NUM_CTP-1:0]`	CTP req-out pad input.
`xtrig_ctp_req_out_din_en_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP req-out pad input enable.
`xtrig_ctp_req_in_dout_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP req-in pad data.
`xtrig_ctp_req_in_dout_en_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP req-in pad output enable.
`xtrig_ctp_req_in_din_i`	input	`logic [XTRIG_NUM_CTP-1:0]`	CTP req-in pad input.
`xtrig_ctp_req_in_din_en_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP req-in pad input enable.
`xtrig_ctp_ack_in_dout_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP ack-in pad data.
`xtrig_ctp_ack_in_dout_en_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP ack-in pad output enable.
`xtrig_ctp_ack_in_din_i`	input	`logic [XTRIG_NUM_CTP-1:0]`	CTP ack-in pad input.
`xtrig_ctp_ack_in_din_en_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP ack-in pad input enable.
`xtrig_ctp_ack_out_dout_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP ack-out pad data.
`xtrig_ctp_ack_out_dout_en_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP ack-out pad output enable.
`xtrig_ctp_ack_out_din_i`	input	`logic [XTRIG_NUM_CTP-1:0]`	CTP ack-out pad input.
`xtrig_ctp_ack_out_din_en_o`	output	`logic [XTRIG_NUM_CTP-1:0]`	CTP ack-out pad input enable.
`test_en_i`	input	`logic`	DFT test-mode enable, active-high, for the JTAG2AXI bridges and the CTN CSR crossbar.
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low; unused. DTP has no reset synchronizer, so rst_n_i must arrive scan-controlled.