aes_wrapper

Wrap the OpenTitan AES core with an AXI-Lite CSR bridge and a Key Manager key CSR block.

axi_lite_to_tlul bridges the 32-bit AXI-Lite CSR interface onto the AES TL-UL port. The AXI4-Lite key interface terminates in the generated aes_wrapper_key_reg block, whose two key shares and valid bit drive the AES keymgr_key_i sideload port. EDN supplies entropy for PRNG reseeding. Two alerts leave the block: index 0 is recoverable (recov_ctrl_update_err) and index 1 is fatal (fatal_fault). The shadow-register reset is tied to rst_ni, lifecycle escalation is tied off, and the EDN clock is clk_i. bus_err_o sticks on a TL-UL error response until bus_err_clr_i. idle_o reports AES idle.

Ports

Table 1. Ports
NameDirectionTypeDescription
clk_iinputlogicSystem clock.
rst_niinputlogicActive-low reset; also drives the AES shadow-register reset.
aes_axil_req_iinputsep_pkg::sep_32_32_axil_req_tAES CSR request, bridged to the AES TL-UL port.
aes_axil_resp_ooutputsep_pkg::sep_32_32_axil_resp_tAES CSR response from the TL-UL bridge.
aes_key_axil_req_iinputsep_pkg::sep_32_32_axil_req_tKey Manager private-bus request to the AES key CSR block.
aes_key_axil_resp_ooutputsep_pkg::sep_32_32_axil_resp_tResponse from the AES key CSR block to the Key Manager.
edn_req_ooutputedn_pkg::edn_req_tEDN request for PRNG reseeding entropy.
edn_rsp_iinputedn_pkg::edn_rsp_tEDN response for PRNG reseeding entropy.
alert_rx_iinputprim_alert_pkg::alert_rx_t [1:0]Alert receiver handshakes; index 0 recoverable (recov_ctrl_update_err), index 1 fatal (fatal_fault).
alert_tx_ooutputprim_alert_pkg::alert_tx_t [1:0]Differential alert senders; index 0 recoverable (recov_ctrl_update_err), index 1 fatal (fatal_fault).
bus_err_ooutputlogicSet by a TL-UL error response on the CSR bridge; sticky until bus_err_clr_i.
bus_err_clr_iinputlogicClears bus_err_o; a fault in the same cycle still sets it.
idle_ooutputlogicHigh when the AES core reports idle (mubi4 strictly true).