hmac_wrapper
Wrap the OpenTitan HMAC core with an AXI-Lite CSR bridge and a Key Manager key CSR block.
axi_lite_to_tlul bridges the 32-bit AXI-Lite CSR interface onto the HMAC TL-UL port. CSR addresses are rebased by the low 13 bits of the SEP HMAC base address and masked to the 13-bit HMAC window before the bridge. The AXI4-Lite key interface from the Key Manager private bus terminates in the generated hmac_wrapper_key_reg block, whose two key shares and valid bit drive the HMAC keymgr_key_i sideload port. One fatal alert (fatal_fault) leaves the block. bus_err_o sticks on a TL-UL error response until bus_err_clr_i. idle_o reports HMAC idle.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | logic | System clock. |
rst_ni | input | logic | Active-low reset. |
hmac_axil_req_i | input | sep_pkg::sep_32_32_axil_req_t | HMAC CSR request at system addresses; rebased and masked to 13 bits before the TL-UL bridge. |
hmac_axil_resp_o | output | sep_pkg::sep_32_32_axil_resp_t | HMAC CSR response from the TL-UL bridge. |
hmac_key_axil_req_i | input | sep_pkg::sep_32_32_axil_req_t | Key Manager private-bus request to the HMAC key CSR block. |
hmac_key_axil_resp_o | output | sep_pkg::sep_32_32_axil_resp_t | Response from the HMAC key CSR block to the Key Manager. |
intr_hmac_done_o | output | logic | HMAC done interrupt. |
intr_fifo_empty_o | output | logic | HMAC message FIFO empty interrupt. |
intr_hmac_err_o | output | logic | HMAC error interrupt. |
alert_rx_i | input | prim_alert_pkg::alert_rx_t [0:0] | Alert receiver handshake for the single fatal alert (fatal_fault). |
alert_tx_o | output | prim_alert_pkg::alert_tx_t [0:0] | Differential alert sender for the single fatal alert (fatal_fault). |
bus_err_o | output | logic | Set by a TL-UL error response on the CSR bridge; sticky until bus_err_clr_i. |
bus_err_clr_i | input | logic | Clears bus_err_o; a fault in the same cycle still sets it. |
idle_o | output | logic | High when the HMAC core reports idle (mubi4 strictly true). |