kmac_wrapper

Wrap the OpenTitan KMAC core with an AXI-Lite CSR bridge and a Key Manager key CSR block.

axi_lite_to_tlul bridges the 32-bit AXI-Lite CSR interface onto the KMAC TL-UL port. CSR addresses are rebased by the low 12 bits of the SEP KMAC base address and masked to the 12-bit KMAC window before the bridge. The AXI4-Lite key interface from the Key Manager private bus terminates in the generated kmac_wrapper_key_reg block, whose two key shares and valid bit drive the KMAC keymgr_key_i sideload port. EDN supplies entropy for the PRNG. Two alerts leave the block: index 0 is recoverable (recov_operation_err) and index 1 is fatal (fatal_fault_err). The hardware application interfaces are tied off, the shadow-register reset is tied to rst_ni, lifecycle escalation is tied off, and the EDN clock is clk_i. bus_err_o sticks on a TL-UL error response until bus_err_clr_i. idle_o reports KMAC idle.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset; also drives the KMAC shadow-register reset.
`kmac_axil_req_i`	input	`sep_pkg::sep_32_32_axil_req_t`	KMAC CSR request at system addresses; rebased and masked to 12 bits before the TL-UL bridge.
`kmac_axil_resp_o`	output	`sep_pkg::sep_32_32_axil_resp_t`	KMAC CSR response from the TL-UL bridge.
`kmac_key_axil_req_i`	input	`sep_pkg::sep_32_32_axil_req_t`	Key Manager private-bus request to the KMAC key CSR block.
`kmac_key_axil_resp_o`	output	`sep_pkg::sep_32_32_axil_resp_t`	Response from the KMAC key CSR block to the Key Manager.
`edn_req_o`	output	`edn_pkg::edn_req_t`	EDN request for PRNG entropy.
`edn_rsp_i`	input	`edn_pkg::edn_rsp_t`	EDN response for PRNG entropy.
`intr_kmac_done_o`	output	`logic`	KMAC done interrupt.
`intr_fifo_empty_o`	output	`logic`	KMAC message FIFO empty interrupt.
`intr_kmac_err_o`	output	`logic`	KMAC error interrupt.
`alert_rx_i`	input	`prim_alert_pkg::alert_rx_t [1:0]`	Alert receiver handshakes; index 0 recoverable (recov_operation_err), index 1 fatal (fatal_fault_err).
`alert_tx_o`	output	`prim_alert_pkg::alert_tx_t [1:0]`	Differential alert senders; index 0 recoverable (recov_operation_err), index 1 fatal (fatal_fault_err).
`bus_err_o`	output	`logic`	Set by a TL-UL error response on the CSR bridge; sticky until bus_err_clr_i.
`bus_err_clr_i`	input	`logic`	Clears bus_err_o; a fault in the same cycle still sets it.
`idle_o`	output	`logic`	High when the KMAC core reports idle (mubi4 strictly true).